Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-09-03
2001-04-17
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S756000, C438S239000
Reexamination Certificate
active
06218723
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits, and, more particularly, to an integrated circuit capacitor.
BACKGROUND OF THE INVENTION
It is common practice to make integrated circuits having one or more high capacitance capacitors. These integrated circuit capacitors advantageously replace conventional capacitors which are discrete components. Integrated circuit capacitors have various applications in the field of analog or RF circuits. For example, integrated circuit capacitors can be used for the filtering of supply voltages, the making of LC type antenna circuits, etc. Among known integrated circuit capacitors are polysilicon/oxide/polysilicon type capacitors providing various advantages, such as low series resistance, high value per surface unit, low variation as a function of temperature. In addition, these integrated circuit capacitor provides under certain conditions high linearity as a function of voltage, i.e., a substantially constant value regardless of the voltage applied.
FIG. 1
is a partial sectional view of a capacitor C
0
of the above-mentioned type integrated into a silicon chip. The capacitor has electrodes
1
,
2
made of polysilicon separated by a thin layer
3
of silicon oxide. Polysilicon hereinafter designates polycrystalline silicon. The upper electrode
2
is covered with a silicide layer
4
, which is generally a metal silicide such as titanium silicide TiSi
2
. The upper electrode
2
is furthermore provided with an electrical contact
5
, such as a metallized zone or a conductive track, for example. The capacitor C
0
is made on a thick silicon oxide layer
6
deposited on a silicon substrate
7
. The thin oxide layer
3
has a small thickness, typically about 30 nanometers, and the electrodes
1
,
2
have a thickness of about 200 to 300 nanometers. The electrodes
1
,
2
are doped with arsenic or phosphorus, and thus have an N-type doping.
As is well known to those skilled in the art, polysilicon has a low electrical conductivity when highly doped. The layer of metal silicide
4
, in contrast, has high conductivity and enables this drawback to be overcome. Thus, when there is no silicide treatment, a polysilicon/oxide/polysilicon integrated capacitor shows high series resistance which proves to be a problem in AC operation, especially in an LC resonant circuit wherein the circuit's Q factor it modified.
Furthermore, it is known that obtaining a capacitor with high voltage linearity requires that the electrodes should be highly doped, so that limits may be placed on the presence in the polysilicon of a depletion zone that counters the passage of the current. Thus, an ideal integrated circuit capacitor has highly doped silicon electrodes and a silicide layer on its upper electrode. A capacitor of this type has high voltage linearity and low series resistance.
The making of a capacitor of this type that has intensive doping of the upper electrode is incompatible with the process of applying silicide treatment to the electrode, which is done at a moderate temperature in the presence of a metal. This is because the dopant slows down the diffusion of silicon in the metal and may even block the entire process. Thus, it often happens that a highly doped polysilicon layer, after being subjected to silicide treatment, has zones that are entirely devoid of silicide. Furthermore, the dopant concentration in the upper electrode gets substantially diminished during the process of silicide treatment through the migration of dopants into the silicide layer under formation. Consequently, these various factors mean that a compromise is required for making a capacitor which has a medium doped upper electrode that is well suited to the silicide treatment process, but which has a voltage linearity that is not optimum.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a capacitor that provides both optimum voltage linearity and minimum series resistance.
To achieve this object, the surface concentration of dopant is made independent of the polysilicon electrode. The dopant concentration at the interface with the silicon oxide dielectric is distinct from the dopant concentration on the surface to be given the silicide treatment. The integrated circuit capacitor is preferably integrated on a silicon substrate comprising a first electrode made of highly doped polysilicon, a thin silicon oxide layer, a second electrode made of polysilicon, and a silicide layer covering the second electrode. The second electrode preferably has a high dopant concentration at its interface with the silicon oxide and a low or medium dopant concentration at its interface with the silicide.
According to a first embodiment of an integrated circuit capacitor, the second electrode comprises at least two polysilicon layers that do not have the same dopant concentration. The second electrode comprises a first polysilicon layer that is highly doped and placed on the oxide side, and a second layer of weakly or medium doped polysilicon. Preferably, the first polysilicon layer has a dopant concentration in the range of 4E
20
to 8E
20
atoms/cm
3
, and the second polysilicon layer has a dopant concentration in the range of 1E
20
to 2E
20
atoms/cm
3
.
According to a second embodiment of an integrated circuit capacitor, the two polysilicon layers are separated by a thin metal layer. According to one alternative, the thin metal layer is a metal selected from the group comprising titanium, tungsten, cobalt and tantalum. According to another alternative, the thin metal layer comprises two thin layers of two different metals or alloys. Preferably, the thin metal layer comprises a layer of titanium and a layer of titanium nitride.
According to a third embodiment of an integrated circuit capacitor, the second electrode comprises a polysilicon layer having a profile of dopant concentration that decreases from its interface with the silicon oxide towards its interface with the silicide. Preferably, the dopant concentration of the second electrode is in the range of 4E
20
to 8E
20
atoms/cm
3
on the oxide side, and in the range of 1E
20
to 2E
20
atoms/cm
3
on the silicide layer side.
During the making of an integrated circuit capacitor according to the invention, it is preferable that the silicide layer covering the second electrode is formed of a metal selected from the group consisting of titanium, tungsten, cobalt and tantalum.
REFERENCES:
patent: 5343062 (1994-08-01), Tomioka
patent: 5510637 (1996-04-01), Hsu et al.
patent: 5721152 (1998-02-01), Jeng et al.
patent: 5744853 (1998-04-01), Quek et al.
patent: 5840605 (1998-11-01), Tuan
patent: 2 294 586 (1996-01-01), None
Delpech Philippe
Dutartre Didier
Robilliart Etienne
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Hardy David
STMicroelectronics S.A.
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