Integrated capacitor on the back of a chip

Details Integrated capacitor on the back of a chip Integrated capacitor on the back of a chip

1999-09-20

2002-04-16

Tran, Minh Loan (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S691000, C257S666000, C257S707000, C257S719000, C257S784000, C361S734000, C361S723000

Reexamination Certificate

active

06373127

ABSTRACT:

FIELD OF THE INVENTION
This invention is related to an integrated circuit device and more particularly to an integrated circuit with an integral de-coupling capacitor, and to a method of manufacture.
BACKGROUND OF THE INVENTION
As the integrated circuit industry moves toward higher circuit density and larger memory sizes, more stringent requirements are being placed on noise suppression and noise filtering systems which are typically located on the printed circuit board. De-coupling, or bypass capacitors are necessary to provide a temporary supply of charge to the integrated circuit as the output of power supplies connected to the integrated circuit varies. In this way, circuit operation is not compromised due to a temporary drop in voltage supply. To enhance de-coupling, these bypass capacitors need to be as close to the device as possible in order for the inductance between the capacitors and devices to be as small as possible.
Integrated circuits of higher densities and larger memory sizes have thinner dielectric between their internal interconnect levels. As such, those circuits are much more susceptible to damage from noise spikes on power lines of the power supplies.
As the circuits have increased the number of power supplies has also increased resulting in a need for more capacitors with greater values. Moreover, as frequency handling characteristics differ for different capacitors, a single capacitor cannot handle both low end frequency and high end frequency noise suppression adding further to the need for multiple capacitors, which In turn results in increasing the circuit board space required.
Attempts have been made to conserve board space and to bring capacitors closer to the integrated circuit devices by incorporating capacitors within the IC package.
FIG. 1
a
illustrates a cross section of a conventional package in which an integrated circuit chip
11
is wire bonded
14
to a leadframe
13
, and is encapsulated by a molded polymer
18
. An inside view of the package is shown in
FIG. 1
b
, including a leadframe
13
, a semiconductor device
11
represented by dashed lines adhered to a mount support pad
12
, and power supply busses
16
and
17
. Power supply bus
16
delivers Vss and power supply bus
17
delivers Vdd. The power supply busses are physically spaced apart, and the de-coupling capacitor
19
lies underneath the mount pad
12
. The capacitor is a long terminal device having its electrodes connected between Vss
16
and Vdd
17
. This does not provide a practical solution to the problem at hand because only one capacitor can be included in the package, and because the long device can cause reliability problems from undue stresses on the encapsulating plastic, and on the capacitor itself.
FIG. 2
shows an alternate approach of prior art having a de-coupling capacitor within the semiconductor package. The backside of the semiconductor chip
21
is used as one electrode of the de-coupling capacitor and the leadframe mount pad
22
becomes the second terminal. A lead
24
is connected directly to the mount pad
22
for external contact. The chip is wire bonded to the leads
23
, one of which will be the external contact for the first terminal. An adhesive (not shown) may become the dielectric between the terminals. This approach would require a leadframe designed specifically for the device wherein the mount pad is connected to Vdd or alternately to Vss (depending on the chip doping). It could be applicable only to conventional packaging in which the chip is attached to a leadframe using an electrically insulating adhesive which lacks the thermal conductivity of metal filled mount compounds typically used in the industry. While the value of the capacitor could be large with this approach, it is limited to a single capacitor per semiconductor package.
Yet another approach for incorporating de-coupling capacitors in a lead-on-chip semiconductor device has been disclosed in U.S. Pat. No. 5,115,298 issued May 19, 1992 and is incorporated herein by reference. As demonstrated in
FIGS. 3
a
and
3
b
the active surface of a semiconductor chip
31
is adhered by an insulating tape
33
to a leadframe having power supply busses Vdd
36
and Vss
37
which are parallel and extend the length of the lead frame in close proximity to each other. Electronic devices
39
, such as capacitors, are attached to Vdd and Vss near the ends of the power supply busses. By choosing the capacitance of each device, both high end and low end frequency noise suppression can occur simultaneously.
As integrated circuit applications have evolved, much smaller and thinner devices are required. It would be advantageous to provide a reliable means for incorporating de-coupling capacitors into the integrated circuit package. It would be highly desirable that the capacitors require no additional space, and are amenable with evolving packaging and interconnection advances.
SUMMARY OF THE INVENTION
A semiconductor device is disclosed which includes an integrated circuit chip having a integral de-coupling capacitor on the backside of the chip, and which is a part of the chip itself.
The primary objective of the invention is to provide an integral de-coupling capacitor on the backside of the chip including a metal layer, a high dielectric constant layer, and a second layer of metal.
A further object of the invention is to provide multiple integral de-coupling capacitors on an integrated circuit chip.
It is still a further object of the invention to provide de-coupling capacitors which require no additional space on the printed circuit board, and which impart no significant mechanical stresses on the integrated circuit chip, package, or the capacitor itself.
It is an object of this invention to provide integral de-coupling capacitor with high capacitance value.
It is an object of this invention to provide a reliable de-coupling capacitor having an inorganic dielectric which is not hygroscopic.
It is an object of this invention to provide an integrated circuit device having improved thermal dissipation, and having an integral de-coupling capacitor on the backside of the chip.
Yet another object of this invention is to provide a semiconductor device having an integral de-coupling capacitor on the backside of an integrated circuit chip, and the chip with integral capacitors assembled into different package types; conventional leadframes and lead-on-chip molded packages, and board-on-chip ball grid array packages are exemplary.
The integral de-coupling capacitor includes a first layer of metal in intimate contact with the semiconductor substrate of an integrated circuit, a layer of high dielectric constant material, and a second metal layer. The second or exposed metal layer is contacted to a power supply on the integrated circuit. Multiple capacitors are formed by scribing the second metal layer and contacting each capacitor to a power supply of the integrated circuit. High capacitance values are made possible as a function of their large area. Effective capacitors result from close proximity to the active circuits, and by eliminating high inductance interconnections.
A cost effective method for making the integrated circuit chip with integral de-coupling capacitors, and for assembly into different package types is also disclosed.
The drawings constitute a part of this specification and include exemplary embodiments to the invention which may be embodied in various forms. It is to be understood that in some instances aspects of the invention may be shown exaggerated or enlarged to facilitate an understanding of the invention.


REFERENCES:
patent: 5734198 (1998-03-01), Stave
patent: 6054754 (2000-04-01), Bissey

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