Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2000-03-16
2002-01-01
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S396000, C438S484000
Reexamination Certificate
active
06335206
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device having oxide dielectrics, and also relates to a method of fabricating the semiconductor device.
BACKGROUND ART
A memory device incorporating a related ferroelectric condenser is known in the field of semiconductor devices having oxide dielectrics. This related ferroelectric condenser is composed such that a ferroelectric, which is a type of oxide dielectric, is interposed between an upper and a lower electrode.
FIGS. 7A
to
8
B are cross-sectional views showing a related method of fabricating the related ferroelectric condenser used in the above-described memory device.
During fabrication of the related ferroelectric condenser, as shown in
FIG. 7A
, an insulating film
4
is formed on a substrate
2
having CMOS and other elements (not shown). A platinum layer
6
is then formed by depositing platinum on the insulating film
4
by means of sputtering. In the same manner, as shown in
FIGS. 7B
to
7
C, a ferroelectric layer
8
and then a platinum layer
10
are formed on the platinum layer
6
.
Next, as shown in
FIG. 8A
, an upper electrode
12
is formed by conducting RIE (Reactive Ion Etching) on the platinum layer
10
, using a resist as a mask. In the same manner, as shown in
FIGS. 8B
to
8
C, etching is successively conducted on the ferroelectric layer
8
and the platinum layer
6
using another resist (not shown) as a mask, so that a ferroelectric section
14
and a lower electrode
16
can be formed. Finally, an insulating film (not shown) is formed to cover the substrate
2
.
However, problems associated with RIE etching may be encountered during fabrication of the related ferroelectric condenser. That is, the ferroelectric section
14
is formed by conducting RIE etching on the deposited ferroelectric layer
8
. The RIE etching causes ions to shock the ferroelectric section
14
, resulting in the ferroelectric section
14
having a tendency to develop a lattice defect. There is also a tendency for the RIE etching to cause a reducing reaction in the ferroelectric section
14
. Accordingly, ferroelectricity, which is a function of the ferroelectric section
14
, tends to deteriorate. These problems are especially serious in the case of a highly integrated memory device in which the area of the ferroelectric section
14
is small.
It is an object of the present invention to overcome the above-described problems by providing a semiconductor device characterized in that an operation of the oxide dielectric section (e.g., a ferroelectric) is seldom deteriorated. It is a further object of the present invention to provide a method of fabricating the semiconductor device.
In the related method of fabricating the related ferroelectric condenser, the following problems may be encountered. In order to prevent a product of etching (i.e., a side wall polymer), which is difficult to be removed, from adhering to a side
14
a
of the ferroelectric section
14
when RIE etching is conducted on the ferroelectric layer
8
, a ratio of isotropic etching is set at a high value. Accordingly, the side face
14
a
of the ferroelectric section
14
is greatly inclined. This inclination results in the area required for the ferroelectric section
14
to be unnecessarily increased, which in turn obstructs the enhancement of the degree of integration of the semiconductor device into which the ferroelectric condenser is incorporated.
Further, when consideration is given to the fluctuation of the etching condition, it is necessary to provide a large margin between the ferroelectric section
14
and the upper electrode
12
, or between the ferroelectric section
14
and the lower electrode
16
.
It is another object of the present invention to solve the above problems by providing a semiconductor device having a degree of integration that can be easily enhanced. It is a further object of the present invention to provide a method of fabricating such a semiconductor device.
DISCLOSURE OF THE INVENTION
In the first aspect of the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of: forming an insulating layer on a semiconductor substrate including a first layer; forming a through hole in the insulating layer so as to reach for the first layer; charging an oxide dielectric substance into the through hole to form an oxide dielectric section therein; and forming a second layer on the oxide dielectric section.
When an oxide dielectric substance is charged into the through hole, the oxide dielectric section, having the same shape as the internal shape of the through hole, is formed. Thus, the oxide dielectric section can be formed into a predetermined shape without etching. It is therefore possible to avoid the occurrence of a lattice defect and a reducing reaction, which are caused by etching the oxide dielectric section. As a result, the function of the oxide dielectric section is seldom deteriorated.
When the shape of the through hole is determined, the shape of the oxide dielectric section is thus determined. Accordingly, as compared with a case in which the shape of the oxide dielectric section is determined by etching, fluctuation of the shape of the oxide dielectric section is reduced. Therefore, it is possible to reduce a margin for absorbing the fluctuation and enhance a grade of integration of the device.
When the shape of the through hole is determined, a contact area between the first layer and the oxide dielectric section is thus determined. Accordingly, fluctuation of the contact area is reduced. In case it is constituted a condenser wherein the first layer serves as a lower electrode, capacity fluctuation thereof can be reduced.
In this connection, a method of forming the through hole in the insulating layer is not particularly restricted. For example, even when the well-known etching method is applied, the through hole can be formed with sufficiently high accuracy.
In the second aspect of the present invention, the method further comprises forming the first layer on an upper surface of the semiconductor substrate.
In the third aspect of the present invention the step of forming the oxide dielectric section includes the steps of laminating the oxide dielectric substance onto the insulating layer while filling the through hole therewith and removing the oxide dielectric substance located areas other than the inside of the through hole.
For example, the step of laminating the oxide dielectric substance is conducted by the sol-gel method and the step of removing the substance is conducted by the CMP (chemical mechanical polishing) method. Accordingly, the oxide dielectric section can be formed with significant ease.
In the fourth aspect of the present invention, the method further comprises the step of patterning the first layer before the step of forming the insulating layer.
Accordingly, in a process in which a layer arranged above the first layer (e.g., the second layer) is patterned by the etching, it is not necessary to conduct a patterning of the first layer lying in the lowermost. That is, in the above step of patterning, it is not necessary to etch deeply. Therefore, irregularities on the upper surface of the device are not so remarkable and can be flattened thereby.
In the fifth aspect of the present invention, the method further comprises the step of planarizing an upper surface of the insulating layer before the step of filling the through hole with the oxide dielectric substance.
Accordingly, when the oxide dielectric substance placed outside of the through hole is removed by, for example, the CMP method, the oxide dielectric substance can be easily and positively removed therefrom.
In the sixth aspect of the present invention, the method further comprises the step of patterning the first layer after the dielectric oxide dielectric section is formed.
Accordingly, in the step of forming the oxide dielectric section, the first layer has not been patterned yet, and the insulating layer formed on the first layer is flat. Therefore, when the oxide dielectr
Lebentritt Michael
Morgan & Lewis & Bockius, LLP
Rohm & Co., Ltd.
LandOfFree
Integrated capacitor device and method of fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated capacitor device and method of fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated capacitor device and method of fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2821113