Integrated capacitance multiplier especially for a temperature c

Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – By integrating

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327553, 327552, G06G 764, H03B 100

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active

060407301

ABSTRACT:
An integrated capacitance multiplier circuit utilizes a pair of field effect transistors, biased in a conducting state, as virtual resistances of a classic operational amplifier network for implementing a capacitance multiplier function. The two field effect transistors have different sizes from each other for attaining a given ON-resistance ratio. A biasing circuit provides independently adjustable biasing voltages for the two field effect transistors. At least one of the two biasing voltages produced by the biasing circuit can be made dependent on temperature according to a certain dependency law in order to exploit the capacitance multiplier circuit for temperature compensating an integrated RC circuit employing the virtual capacitance provided by the multiplier circuit.

REFERENCES:
patent: 3831117 (1974-08-01), Fletcher et al.
patent: 4477737 (1984-10-01), Ulmer et al.
patent: 4587437 (1986-05-01), Schorr
patent: 5006733 (1991-04-01), Brown
patent: 5034626 (1991-07-01), Pirez et al.
patent: 5095227 (1992-03-01), Jeong
patent: 5130571 (1992-07-01), Carroll
IBM Technical Disclosure Bulletin: vol. 31, No. 2, Jul. 1988, p. 414 New York, US In. 15-In. 22.

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