Boots – shoes – and leggings
Patent
1990-11-21
1993-09-28
Bowler, Alyssa H.
Boots, shoes, and leggings
364DIG1, 36424345, 3649646, G06F 1300, G06F 1208
Patent
active
052492826
ABSTRACT:
A central processing unit (10) has a cache memory system (24) associated therewith for interfacing with a main memory system (23). The cache memory system (24) includes a primary cache (26) comprised of SRAMS and a secondary cache (28) comprised of DRAM. The primary cache (26) has a faster access than the secondary cache (28). When it is determined that the requested data is stored in the primary cache (26) it is transferred immediately to the central processing unit (10). When it is determined that the data resides only in the secondary cache (28), the data is accessed therefrom and routed to the central processing unit (10) and simultaneously stored in the primary cache (26). If a hit occurs in the primary cache (26), it is accessed and output to a local data bus (32). If only the secondary cache (28) indicates a hit, data is accessed from the appropriate one of the arrays (80)-(86) and transferred through the primary cache ( 26) via transfer circuits (96), (98), (100) and (102) to the data bus (32). Simultaneously therewith, the data is stored in an appropriate one of the arrays (88)-(94). When a hit does not occur in either the secondary cache (28) or the primary cache (26), data is retrieved from the main system memory (23) through a buffer/multiplexer circuit on one side of the secondary cache (28) and passed through both the secondary cache (28) and the primary cache (26) and stored therein in a single operation due to the line for line transfer provided by the transfer circuits (96)-(102).
REFERENCES:
patent: 4464712 (1984-08-01), Fletcher
patent: 4797814 (1989-01-01), Brenza
patent: 4803621 (1989-02-01), Kelly
patent: 4823259 (1989-04-01), Aichelmann, Jr. et al.
patent: 4870622 (1989-09-01), Aria et al.
patent: 4894770 (1990-01-01), Ward et al.
patent: 4905141 (1990-02-01), Brenza
patent: 4926385 (1990-05-01), Fujishima et al.
patent: 4928239 (1990-05-01), Baum et al.
patent: 4930106 (1990-05-01), Danilenko et al.
patent: 4933835 (1990-06-01), Sachs et al.
patent: 4933837 (1990-06-01), Freidin
patent: 4939641 (1990-06-01), Schwartz et al.
patent: 4953164 (1990-08-01), Asakura et al.
patent: 5023776 (1991-06-01), Gregor
patent: 5058006 (1991-10-01), Durdan et al.
patent: 5077826 (1991-12-01), Grohoski et al.
Benchmarq Microelectronics, Inc.
Bowler Alyssa H.
LandOfFree
Integrated cache memory system with primary and secondary cache does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated cache memory system with primary and secondary cache , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated cache memory system with primary and secondary cache will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2196922