Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1999-07-26
2000-09-19
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257750, 257752, H01L 2348, H01L 2352, H01L 2940
Patent
active
061216844
ABSTRACT:
The present invention provides a structure and method of forming a butting contact having protective spacers 50A that prevent shorting between a second polysilicon layer 60 and the substrate in a hole 20A in a isolation region 20. The following are provide: a isolation region 20, a first conductive line 30B over portions of the isolation region 20, and an inter-poly insulating layer 40. The protective spacers prevent shorts when the first conductive line 30B is misaligned and exposes a first portion of the isolation region 20 in a butt contact opening. A first photoresist layer 44 having a butt contact photoresist opening 44A over the first doped region 26 and over a first portion of the isolation is formed. The inter-poly insulating layer 40 is etched through the butt contact photoresist opening 44A and etches the first portion of the isolation region forming an isolation hole 20A. In an important step, protective spacers 50A are formed on the sidewalls of the isolation hole 20A. A second conductive layer 60 is formed over an inter-poly insulating layer 40, in the butt contact opening, and over the protective spacers 50A. The protective spacers 50A prevent the second conductive layer 60 from contacting the substrate in the hole 20A.
REFERENCES:
patent: 5677231 (1997-10-01), Maniar et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 6046505 (2000-04-01), Howard
Wolf et al., Silicon Processing for the VLSI Era, vol. 2, pp. 160-163.
Ackerman Stephen B.
Owens Douglas W.
Saile George O.
Steffel William J.
Taiwan Semiconductor Manufacturing Company
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