Integrated bus bridge and memory controller that enables data st

Details Integrated bus bridge and memory controller that enables data st Integrated bus bridge and memory controller that enables data st

1995-01-20

1997-05-13

Gossage, Glenn

395474, 395494, 395308, 395309, 395872, G06F 1300, G06F 1340, G06F 300

Patent

active

056300948

ABSTRACT:
A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.

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