Integrated bipolar-CMOS circuit isolation process for providing

Details Integrated bipolar-CMOS circuit isolation process for providing Integrated bipolar-CMOS circuit isolation process for providing

1989-01-06

1990-03-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 56, 437 74, H01L 2122, H01L 21283

Patent

active

049120549

ABSTRACT:
Disclosed is a proces for making a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.

REFERENCES:
patent: 3999213 (1976-12-01), Brandt et al.
patent: 4684970 (1987-08-01), Sloane et al.
patent: 4721682 (1988-01-01), Graham et al.
patent: 4825275 (1989-04-01), Tomasetti

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