Integrated bipolar-CMOS circuit isolation for providing differen

Details Integrated bipolar-CMOS circuit isolation for providing differen Integrated bipolar-CMOS circuit isolation for providing differen

1989-04-11

1991-10-22

Jackson, Jr., Jerome

357 42, 357 34, H01L 2972, H01L 2702

Patent

active

050600443

ABSTRACT:
Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.

REFERENCES:
patent: 4646124 (1987-02-01), Zumino
patent: 4714842 (1987-12-01), Hart et al.

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