Integrated arithmetic unit and digital networks using the unit

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364736, 364758, G06F 1534, G06F 739

Patent

active

041288904

ABSTRACT:
The invention relates to an arithmetic unit fabricated by large scale integration techniques and to an improved digital network of increased accuracy in which the unit finds application. The integrated circuit comprises an initial summing means, rounding means, full precision multiplication logic and three successive summing means, all elements being successively connected, and all except the first having both internal and external input terminals. The unit is flexible in respect to the length of the operands and their sign notation. The terminals are readily cascaded, permitting interconnection of the unit with like integrated circuit units and with external delay elements. The invention is applicable in a variety of complex operations including digital filtering, correlation, convolution, polynomial evaluation and squaring. In many of these applications, mixed precision and rounding provide increased accuracy in the resulting digital networks.

REFERENCES:
patent: 3947670 (1976-03-01), Irwin et al.
patent: 3980873 (1976-09-01), Mattei
patent: 4021654 (1977-05-01), Harris et al.
patent: 4034197 (1977-07-01), Lawrence et al.

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