Integratable switched-capacitor sigma-delta modulator

Details Integratable switched-capacitor sigma-delta modulator Integratable switched-capacitor sigma-delta modulator

1990-05-07

1991-03-12

Shoop, Jr., William M.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341143, H03M 112

Patent

active

049996347

ABSTRACT:
A switched-capacitor sigma-delta modulator includes at least one memory element, at least one comparator, and at least one integrator. The at least one integrator has an input stage including a series circuit of a first switch, a first capacitor and a second switch, a third switch for connecting one of the two terminals of the first capacitor to ground potential, and a fourth switch for connecting the other of the two terminals of the first capacitor to ground potential. A nodal point is connected between the second and fourth switches and the other of the two terminals of the first capacitor. A negative feedback stage includes second and third capacitors each having one terminal connected to the nodal point. A fifth switch connects the other terminal of the second capacitor to a first potential. A sixth switch connects the other terminal of the third capacitor to a second potential. Seventh and eighth series-connected switches connect the other terminal of the second capacitor to the second potential. Ninth and tenth series-connected switches connect the other terminal of the third capacitor to the first potential. The eighth and tenth switches may be omitted. Eleventh and twelfth switches or thirteenth and fourteenth switches may respectively connect the second and third capacitors to one nodal point or to a nodal point symmetrical thereto or visa versa, as a function of the output signal of the memory element.

REFERENCES:
patent: 3251052 (1966-05-01), Hoffman et al.
patent: 3462754 (1969-08-01), Hoffman
patent: 3585634 (1968-06-01), Sharples
patent: 3906488 (1975-09-01), Suarez-Gartner
patent: 4588981 (1986-05-01), Senn
Patent Abstracts of Japan, vol. 9, No. 150 (E-324) (1873), Jun. 25, 1985; & JP-A-60 31 315 (Nippon Denki K. K.), Feb. 18, 1985.
1986 IEEE International Solid-State Circuits Conference, Feb. 20, 1986, Session XIV, pp. 182-183, IEEE, N.Y., US; T. Hayashi et al.: "A Multistage Delta-Sigma Modulator Without Double Integration Loop".
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, Rochester, N.Y., May 16-19, 1988, pp. 21.3.1-21.3.4, IEEE, N.Y., US; S. R. Norsworthy et al.: "A 13-Bit, 160 kHz Sigma-Delta A/D Converter for ISDN".
Electronic Letters, Feb. 17, 1983, vol. 19, No. 4, pp. 149-150; G. Lainey et al.: "Switched-Capacitor Second-Order Noise-Shaping Coder".

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