Integratable phase-locked loop

Details Integratable phase-locked loop Integratable phase-locked loop

1990-05-15

1992-04-21

Pascal, Robert J.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Transistorized controls

331 17, H03L 700

Patent

active

051072270

DESCRIPTION:

BRIEF SUMMARY
RELATED APPLICATIONS

The specification lodged in respect of this application is a cognate of the disclosures in Australian Provisional Patent Application No. PI 5477, entitled "Integratable Phase Locked Loop", filed Nov, 18, 1987, and Australian Provisional Patent Application No. PI 6631, entitled "Calibrator", filed Feb. 8, 1988, and Australian Provisional Patent Application No. PI 7879, entitled "A Modified Oscillator And Integratable Phase Locked Loop", filed Apr. 22, 1988, all the aforementioned Applications having been lodged in the name of the present Applicant.


FIELD OF INVENTION

The present invention relates to an integratable phase-locked loop (IPLL) for use in electrical or electronic circuit applications. More specifically, the present invention relates to a phase-locked loop (PLL) suitable for Very Large Scale Integration (VLSI implementation). Most specifically, the present invention relates to a substantially totally integratable PLL. The IPLL of the present invention has application in frequency synthesis and signal demodulation.


PRIOR ART

A prior art Phase Locked Loop (PLL) comprises at least three elements; a Voltage (or Current) Controlled Oscillator (VCO), a Phase Detector or Comparator (PD), and a Low Pass Filter (LPF). These elements are connected in a ring formation, whereby the PD measures the difference in phase between an external Reference signal and the VCO's output, and this difference filtered by the LPF serves to adjust the frequency of the VCO, so as to keep it in synchronism with the Reference signal. Optionally, a Frequency Divider may be connected at the output of the VCO, which then runs at a multiple of the Reference frequency, and the entire PLL constitutes a frequency multiplier. This type of circuit is described, inter alia, in "Phase-Locked Loops: Theory, Design & Applications", Best R. E., McGraw Hill 1984. FIG. 1 shows a prior art PLL.
Other prior art PLL circuits are exemplified by "Hochschild" in U.S. Pat. No. 4,538,282, "Klinkovsky, Severin" in U.S. Pat. No. 4,571,731, and "Fried" in U.S. Pat. No. 4,626,798.
Prior art PLL's known to Applicant do not in fact achieve the goal of total integration, in that they integrate many but not all components on the VLSI chip.
U.S. Pat. No. 4,626,798 discloses a PLL which achieves total integration, but it is only suitable for use at extremely high frequencies (quoted as above 100 MHz). Not only are lower frequencies more commonly required, but very high frequencies require specialised circuit techniques, for example Emitter-Coupled Logic, which is both costly to produce and consumes large amounts of electrical power in use. At the high frequencies disclosed in U.S. Pat. No. 4,626,798, use is made of the resistance of the ordinary circuit wiring to form the LPF, (page 5, lines 45 to 50). This is not available at lower frequencies, where the values required for such resistors become excessive. Further, the electrical value of such wiring resistance is poorly controlled in most practical VLSI fabrication processes, which can lead to poor control of the LPF characteristics. This may lead to unpredictable behaviour in the presence of changes (e.g. modulation) in the Reference input signal. A mathematical analysis in the book by "Best" referred to above shows that even small changes in the LPF characteristics may, in some cases, prevent the PLL from ever acquiring lock, or require an excessive time to acquire lock.
The disadvantages of very high frequency operation, as noted above, will equally apply where a moderate-frequency PLL is to be realised by building a very high frequency PLL, and passing the output through a frequency divider to achieve a moderate frequency output.
U.S. Pat. No. 4,538,282 discloses a PLL which utilises the so-called "digital VCO" concept, whereby the adjustable frequency from the VCO is obtained by passing a constant, high-frequency input through a variable frequency-divider circuit. The output frequency is then the original high frequency divided by the modulus of the divider circuit. Such a sys

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