Adhesive bonding and miscellaneous chemical manufacture – Methods – Surface bonding and/or assembly therefor
Reexamination Certificate
1999-05-04
2003-09-09
Ball, Michael W. (Department: 1733)
Adhesive bonding and miscellaneous chemical manufacture
Methods
Surface bonding and/or assembly therefor
C156S307300, C501S137000, C361S762000, C361S763000
Reexamination Certificate
active
06616794
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention (Technical Field)
The present invention relates to providing capacitance in printed circuit boards, more specifically to a method and apparatus for providing a layer or layers of integral capacitance in printed circuit boards using dielectric nanopowders.
2. Background Art
Printed circuit boards (PCBs) typically are constructed in a laminated form. Several layers of laminate are used in a board for providing electrical connections to and among various devices located on the surface of the board. These surface devices consist of integrated circuits and discrete passive devices, such as capacitors, resistors and inductors, and the like. The discrete passive devices occupy a high percentage of the surface area of the complete PCB. Therefore, in order to increase the available surface of the PCBs, there have been a variety of past efforts to locate passive devices, including capacitors, in a embedded, or subsurface, configuration within the board. When passive devices are in such a configuration, they are known collectively and individually in the art as “integral passives.” A capacitor designed for disposition within (between the lamina) of a PCB is called an “integral capacitor” and provides “integral capacitance.” If integral capacitive devices are to result in significant contributions to the overall power operations in integrated circuits, advances in the energy storage capabilities of these devices must be made.
There have been past attempts to provide integral capacitance. One example of an invention providing for integral capacitance is in U.S. Pat. No. 5,079,069 to Howard, et al., where a dielectric sheet is sandwiched between conducting sheets to provide a layer of integral capacitance. Currently in such configurations the materials consist of conventional PCB laminate resins such as epoxy, and provide a dielectric sheet with a dielectric constant of approximately 4.5. With thicknesses of approximately 2 mils, such material can provide planar capacitance values of approximately 500 picofarads per square inch. However, many applications require capacitance values much greater than 500 picofarads per square inch and therefore other approaches must provide capacitance layers having higher planar capacitance values.
For a fixed capacitor area, only two approaches are available for increasing the planar capacitance (capacitance/area) of an integral capacitor. First, higher dielectric constant materials can be used. Second, the thickness of the dielectric can be reduced. These constraints are reflected in the following formula, known to the art, for capacitance per area:
C
p
/A
=(∈∈
0
)/
t
where: C
p
=capacitance, A=area of capacitor, ∈=dielectric constant of laminate, ∈
0
= dielectric constant of vacuum, and t=thickness of the dielectric.
Prior efforts in this regard have sought to provide a high capacitance core using laminate a filler having a high dielectric constant. An example, U.S. Pat. No. 5,162,977 suggests how to enhance the capacitance of a dielectric layer using pre-fired and ground ceramic nanopowder, and purports to teach how to produce capacitance values that are four orders of magnitude greater than those achieved simply using epoxy dielectrics. However, using pre-fired and ground ceramic nanopowders in the dielectric layer poses obstacles for the formation of vias (holes permitting electronic communication between layers of a laminated PCB). Pre-fired and ground ceramic nanopowder particles have a typical dimension in the range of 500-20,000 nanometers (nm). Furthermore, the particle distribution in this range is generally rather broad, meaning that there could be a 10,000 nm particle alongside a 500 nm particle. The distribution within the dielectric layer of particles of different size often presents major obstacles to microvia formation, due to the presence of the larger particles. Another problem associated with pre-fired ceramic nanopowders is the ability for the dielectric layer to withstand substantial voltage without breakdown occurring across the layer. Typically, capacitance layers within a PCB are expected to hold off at least 300 V in order to qualify as a reliable component for PCB construction. The presence of the comparatively larger ceramic particles in pre-fired ceramic nanopowders within a capacitance layer prevents ultrathin layers from being used because the boundaries of contiguous large particles provide a path for voltage breakdown. This is doubly unfortunate because, as indicated by the equation above, greater planar capacitance may also be achieved by reducing the thickness of the dielectric layer—with the thinness limited by the size of the particles therein. Accordingly, any process which uniformly disperses very fine uniform dielectric nanopowders within a binder, such as epoxy, leads to capacitance layers which are more compatible with desired microvia formations and can withstand high voltages for thinner layers.
Most commercially available dielectric powders, such as metal titanate-based powders, are produced by a high-temperature, solid-state reaction of a mixture of the appropriate stoichiometric amounts of the oxides or oxide precursors (e.g., carbonates, hydroxides or nitrates) of barium, calcium, titanium, and the like. In such calcination processes, the reactants are wet milled to accomplish an intimate mixture. The resulting slurry is dried and fired at elevated temperatures, as high as 1300° C., to attain the desired solid state reactions. Thereafter, the fired product is milled to produce a powder.
Although the pre-fired and ground dielectric formulations produced by solid phase reactions are acceptable for many electrical applications, they suffer from several disadvantages. First, the milling step serves as a source of contaminants, which can adversely affect electrical properties. Second, the milled product consists of irregularly shaped fractured aggregates which are large in size and possess a wide particle size distribution, 500-20,000 nm. Consequently, films produced using these powders are limited to thicknesses greater than the size of the largest particle. Thirdly, powder suspensions or composites produced using pre-fired ground ceramic powders must be used immediately after dispersion, due to the high sedimentation rates associated with large particles. The stable crystalline phase of barium titanate for particles greater than 200 nm is tetragonal and, at elevated temperatures, a large increase in dielectric constant occurs due to a phase transition.
A need remains for a method and apparatus for providing integral capacitors which employ improved materials to allow for thinner, purer, dielectric layers to boost capacitance and permit reliable creation of microvias.
SUMMARY OF THE INVENTION (DISCLOSURE OF THE INVENTION)
The invention relates to methods and apparatuses for providing integral capacitance within printed circuit boards. According to the invention, there is a method for producing a high capacitance core element for integral inclusion in a printed circuit board comprising the steps of preparing a composite mixture by mixing a bonding matrix material with a slurry comprising a suspension of hydrothermally prepared nanopowder; forming the composite mixture into a dielectric layer; and disposing the dielectric layer between two conductive layers. The method optionally further comprises step of dispersing the hydrothermally prepared nanopowder in an organic solvent. The step of dispersing the hydrothermally prepared nanopowder may comprise dispersing the powder in an initial volumetric ratio of between about 20 percent and about 40 percent powder by volume. The method may also further comprise the step of subjecting the nanopowder and the solvent to ultrasonic energy, or the step of milling the nanopowder and the solvent. Further, a surfactant may be mixed with the nanopowder and solvent.
The step of mixing a bonding matrix material preferably comprises mixing a polymer to form a homogeno
Hartman William F.
Law Kristen J.
Slenes Kirk M.
Baker Rod D.
Fain Katy C.
Haran John T
Peacock Deborah A.
TPL, Inc.
LandOfFree
Integral capacitance for printed circuit board using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integral capacitance for printed circuit board using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integral capacitance for printed circuit board using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3108434