Integral bit error rate test system for serial data communicatio

Details Integral bit error rate test system for serial data communicatio Integral bit error rate test system for serial data communicatio

1995-10-20

1998-03-10

Beausoliel, Jr., Robert W.

Excavating

G06F 1100

Patent

active

057269912

ABSTRACT:
A data communication method and apparatus includes an integral bit error rate test system. The system is adapted to receive digital data signals to be transmitted over a communication link and includes a transmitter for transmitting the data signals onto the link. A test signal pattern generator generates a determinable pattern of digital bit test signals which are insertable into an input of the transmitter in place of the digital data signals. A receiver is coupled to the link for receiving the bit test signals and for comparing the received pattern of the bit test signals to the determinable pattern. The bit error rate is computed from the number of bit differences between the transmitted test signals and the determinable pattern.

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patent: 3689884 (1972-09-01), Tew, Jr.
patent: 4428076 (1984-01-01), Schuon
patent: 5289474 (1994-02-01), Purcell et al.

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