Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
1999-11-10
2003-03-25
Ghayour, Mohammad H. (Department: 2734)
Pulse or digital communications
Receivers
Angle modulation
C375S316000, C375S322000
Reexamination Certificate
active
06539066
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrable radio receiver circuit which quadrature downward mixes a received RF signal to a low intermediate frequency (IF). The low IF signal is then IF channel filtered in an analog polypahse filter before being forwarded to an quadrature signal demodulator.
Analog homodyne receivers are used on radio paging receivers, that is to say for so-called pagers, for the radio paging service. The frequency modulation (FM) which is used for this service makes it possible to use AC coupling to suppress static and dynamic offset voltages in such a receiver.
A known circuit, which is integrated in a single chip, for a homodyne receiver used in a pager is described, for example, by J. Wilson, R. Youell, T. Richards, G. Luff, R. Pilaski in the article “A Single Chip VHF and UHF Receiver for Radio aging” in IEEE Journal of Solid State Circuits, Vol. 26, No. Dec. 2, 1991.
In this case, the RF received signal coming from an antenna is supplied, after amplification in an RF amplifier and after being split into two signals with a phase offset of 90° by a phase element, to two first inputs of a quadrature downward mixer. An output signal of an RF oscillator, which is multiplied in a frequency multiplier, is applied to two second inputs of the quadrature downward mixer.
Channel filtering is carried out following amplification in amplifiers by integrated low-pass filters, which are AC-coupled to one another by a capacitor respectively, in a I path, and integrated low-pass filters in a Q path. The signals in the I and Q paths are supplied separately via in each case one limiting amplifier, respectively, to an analog demodulator (“quadricorrelator”), at whose output the demodulated output signal can then be picked off for display.
For radio systems which operate using Gaussian frequency shift keying (GFSK) or Gaussian minimum shift keying (GMSK) modulation, AC coupling is impossible, since most of the energy of the correspondingly modulated signal is concentrated at low frequencies.
A receiver which operates at a low intermediate frequency (low IF) and using digital demodulation is known from a book by J. Crols and M. Steyaert, titled “CMOS Wireless Transceiver Design”, 1997, Kluwer Academic Publishers, pages 52 to 67 as well as pages 114 and 115 in this context for the GSM mobile radio system, which uses GMSK modulation.
Digital demodulation requires a linear signal path as far as the analog/digital converters which, when used in conjunction with a digital European cordless communications (DECT) system should have a resolution of 12-13 bits with a bandwidth of about 800 kHz (bandpass converter). However, with the technologies available at the moment, this can be achieved only with considerable complexity, and at a high cost.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrable radio receiver circuit for frequency-modulated digital signals which overcomes the above-mentioned disadvantages of the prior art devices of this general type.
The invention is based on the object of specifying a receiver circuit for receiving frequency-modulated digital radio signals, that is to say, in particular, FSK, MSK, GFSK and GMSK-modulated signals, in which, on the one hand, static and dynamic offset voltages are reliably suppressed and in which, on the other hand, there is no need for a linear signal path as far as the analog/digital converters, so that the technical complexity can be considerably reduced. In this case, the aim is for it to be possible to produce the receiver using large-scale integration and without using any external IF filters.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrable radio receiver circuit, including:
an antenna for receiving an RF signal being a frequency-modulated digital signal;
a first quadrature signal path, containing:
a first downward mixer receiving and downward mixing the RF signal to a first low intermediate frequency (IF) signal;
an analog polyphase filter disposed downstream of the first downward mixer for channel filtering the first low intermediate frequency signal; and
a first AC coupling;
a second quadrature signal path, containing:
a second downward mixer receiving and downward mixing the RF signal to a second low intermediate frequency (IF) signal;
the analog polyphase filter disposed downstream of the second downward mixer for channel filtering the second low intermediate frequency signal; and
a second AC coupling;
an analog quadrature signal demodulator connected to the first quadrature signal path and the second quadrature signal path, the analog quadrature signal demodulator having an output producing an output signal with a voltage proportional to an input frequency; and
a decision circuit having an adjustable decision threshold receives the output signal and determines digital signal states of the output signal.
The use of a low IF concept allows AC couplings to be used. There is no longer any need for the signal path linearity requirements that involve a high level of technical complexity. It is then possible to use analog filters and an analog demodulator which can be integrated on a substrate or chip.
The downstream decision circuit can also be integrated, so that the radio receiver circuit according to the invention can be produced, overall, using large-scale integration. The radio receiver circuit according to the invention thus results in a combination of the advantageous characteristics of the two proven types of reception circuit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrable radio receiver circuit for frequency-modulated digital signals, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
is a diagrammatic, block circuit diagram of a prior art circuit of a pager; and
FIG. 2
is a block circuit diagram of an exemplary embodiment of a radio receiver circuit, which may be based on large-scale integration, according to the invention.
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“A Single-Chip VHF and UHF Receiver For Radio Paging” (Wilson et al.), in IEEE Journal of Solid-State Circuits, vol. 26, No. 12, dated Dec. 12, 1991.
“CMOS Wireless Transceiver Design” (Crols et al.), Kluwer Academic Publishers, dated 1997, pp. 52-68.
Ghayour Mohammad H.
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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