Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-08-19
2003-02-18
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06523050
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to microprocessors and, more particularly, to a processor architecture employing an improved floating point unit (FPU).
BACKGROUND OF THE INVENTION
The ever-growing requirement for high performance computers demands that computer hardware architectures maximize software performance. Conventional computer architectures are made up of three primary components: (1) a processor, (2) a system memory and (3) one or more input/output devices. The processor controls the system memory and the input/output (“I/O”) devices. The system memory stores not only data, but also instructions that the processor is capable of retrieving and executing to cause the computer to perform one or more desired processes or functions.
The I/O devices are operative to interact with a user through a graphical user interface (“GUI”) (such as provided by Microsoft Windows™ or IBM OS/2™), a network portal device, a printer, a mouse or other conventional device for facilitating interaction between the user and the computer.
Over the years, the quest for ever-increasing processing speeds has followed different directions. One approach to improve computer performance is to increase the rate of the clock that drives the processor. As the clock rate increases, however, the processor's power consumption and temperature also increase. Increased power consumption is expensive and high circuit temperatures may damage the processor. Further, the processor clock rate may not increase beyond a threshold physical speed at which signals may traverse the processor. Simply stated, there is a practical maximum to the clock rate that is acceptable to conventional processors.
An alternate approach to improve computer performance is to increase the number of instructions executed per clock cycle by the processor (“processor throughput”). One technique for increasing processor throughput is pipelining, which calls for the processor to be divided into separate processing stages (collectively termed a “pipeline”). Instructions are processed in an “assembly line” fashion in the processing stages. Each processing stage is optimized to perform a particular processing function, thereby causing the processor as a whole to become faster.
“Superpipelining” extends the pipelining concept further by allowing the simultaneous processing of multiple instructions in the pipeline. Consider, as an example, a processor in which each instruction executes in six stages, each stage requiring a single clock cycle to perform its function. Six separate instructions can therefore be processed concurrently in the pipeline; i.e., the processing of one instruction is completed during each clock cycle. The instruction throughput of an n-stage pipelined architecture is therefore, in theory, n times greater than the throughput of a non-pipelined architecture capable of completing only one instruction every n clock cycles.
Another technique for increasing overall processor speed is “superscalar” processing. Superscalar processing calls for multiple instructions to be processed per clock cycle. Assuming that instructions are independent of one another (the execution of each instruction does not depend upon the execution of any other instruction), processor throughput is increased in proportion to the number of instructions processed per clock cycle (“degree of scalability”). If, for example, a particular processor architecture is superscalar to degree three (i.e., three instructions are processed during each clock cycle), the instruction throughput of the processor is theoretically tripled.
These techniques are not mutually exclusive; processors may be both superpipelined and superscalar. However, operation of such processors in practice is often far from ideal, as instructions tend to depend upon one another and are also often not executed efficiently within the pipeline stages. In actual operation, instructions often require varying amounts of processor resources, creating interruptions (“bubbles” or “stalls”) in the flow of instructions through the pipeline. Consequently, while superpipelining and superscalar techniques do increase throughput, the actual throughput of the processor ultimately depends upon the particular instructions processed during a given period of time and the particular implementation of the processor's architecture.
The speed at which a processor can perform a desired task is also a function of the number of instructions required to code the task. A processor may require one or many clock cycles to execute a particular instruction. Thus, in order to enhance the speed at which a processor can perform a desired task, both the number of instructions used to code the task as well as the number of clock cycles required to execute each instruction should be minimized.
Statistically, certain instructions are executed more frequently than others. If the design of a processor is optimized to rapidly process the instructions that occur most frequently, then the overall throughput of the processor can be increased. Unfortunately, the optimization of a processor for certain frequent instructions is usually obtained only at the expense of other less frequent instructions, or requires additional circuitry, which increases the size of the processor.
As computer programs have become increasingly more graphic-oriented, processors have had to deal more and more with the conversion between integer and floating point representations of numbers. Thus, to enhance the throughput of a processor that must generate data necessary to represent graphical images, it is desirable to optimize the processor to efficiently convert between integer and floating point representations of data.
U.S. Pat. No. 5,257,215 to Poon, issued Oct. 26, 1993, describes a circuit and method for the performing integer to floating point conversions in a floating point unit. The method disclosed, however, requires a two's complement operation for the conversion of negative numbers; a two's complement operation requires additional clock cycles and is thus undesirable if the throughput of the floating point unit is to be optimized.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an efficient system and method for converting numbers from integer notation to floating point notation and a computer system employing the same. Preferably, the optimization of the processor should not require any additional hardware or degrade the performance of the processor in performing tasks other than integer to floating point conversions; in particular, the conversion of negative numbers should not require the performance of a two's complement operation.
SUMMARY OF THE INVENTION
In the attainment of the above primary object, the present invention provides, for use in a processor having a floating point execution core, logic circuitry for, and a method of, converting negative numbers from integer notation to floating point notation. In one embodiment, the logic circuitry includes: (1) a one's complementer that receives a number in integer notation and inverts the received number to yield an inverted number, (2) a leading bit counter, coupled to the one's complementer, that counts leading bits in the inverted number to yield leading bit data, (3) a shifter, coupled to the one's complementer and the leading bit counter, that normalizes the inverted number based on the leading bit data to yield a shifted inverted number, (4) an adder, coupled to the shifter, that increments the shifted inverted number to yield a fractional portion of the received number in floating point notation and overflow data, the adder renormalizing the fractional portion based on the overflow data and (5) exponent generating circuitry, coupled to the leading bit counter and the adder, that generates an exponent portion of the received number in floating point notation as a function of the leading bit data and the overflow data.
The present invention
Dhablania Atul
Lohman Jeffrey A.
Mai Tan V.
National Semiconductor Corporation
LandOfFree
Integer to floating point conversion using one's... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integer to floating point conversion using one's..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integer to floating point conversion using one's... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3181412