Integer multiply instructions incorporating a subresult selectio

Details Integer multiply instructions incorporating a subresult selectio Integer multiply instructions incorporating a subresult selectio

1994-09-02

1996-11-12

Lim, Krisna

Boots, shoes, and leggings

364760, G06F 752

Patent

active

055746764

ABSTRACT:
A computer instruction and apparatus for performing a N-bit by N-bit multiplication and having the ability to select a part of the multiplication result for storage into a result register N-bits wide. A first embodiment of the invention allows a sequence of n-bits from the N-bit by N-bit multiply result to be stored into an N-bit wide register. N+1 to 1 multiplexors are utilized to select which of the multiply result bits are stored into the result register in response to a multiply and select computer instruction. The second preferred embodiment utilizes multiplexors having fewer than N+1 inputs to select discrete subsets of the multiply result bits for storage into the N-bit wide result register. In this manner, less complex multiplexors are required which take less chip area to implement. The third preferred embodiment utilizes multiple sets of multiplexors to select multiple subresults generated by a parallel multiplication operation. The multiple subresults are stored in a single result register. By allowing subresults to be selected and stored as part of the multiply operation, a multiply apparatus according to the present invention is more time and instruction efficient than prior art devices.

REFERENCES:
patent: 4346437 (1982-08-01), Blahut et al.
patent: 5260889 (1993-11-01), Palaniswani
patent: 5426599 (1995-06-01), Machida
Odnert et al., "Architecture and Compiler Enhancements for PA-RISC Workstations", 1991 IEEE.
Hennessy et al., "Computer Architecture A Quantitative Approach", pp. 141, 159, 1990.
James, "Multiplexed Buses: The Indian Wars continue" 1990 IEEE.

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