Insulator structure for amorphous silicon thin-film transistors

Details Insulator structure for amorphous silicon thin-film transistors Insulator structure for amorphous silicon thin-film transistors

1990-07-16

1991-08-20

Carroll, J.

357 2, 357 4, 357 2315, 357 54, H01L 4500, H01L 2722, H01L 2978, H01L 2701

Patent

active

050418882

ABSTRACT:
A thin-film field-effect-transistor (TFT) includes a gate electrode disposed on a substrate; a first thick layer of silicon nitride is disposed on the substrate and over the gate electrode and a second thinner layer of silicon nitride is disposed on the first layer. The first silicon nitride layer has a silicon-to-nitrogen concentration ratio selected to provide optimum structural characteristics, such as high density, high dielectric strength, low etch rate and the like, to the resulting TFT while the second silicon nitride layer has a silicon-to-silicon concentration ratio selected to provide a good electrical interface between the first silicon nitride layer and a subsequently deposited first layer of amorphous silicon. Another layer of doped amorphous silicon is formed on the first amorphous silicon layer and the second doped layer is patterned to form source and drain regions of the TFT. A source electrode and a drain electrode are respectively disposed in contact with the source and drain regions.

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Nam-Deog Kim et al., "Amorphous Silicon Thin-Film Transistors with Two-Layer Gate Insulator", Applied Physics Letters, vol. 54 (May 1989), pp. 2079-2081.
W. A. P. Claassen et al., "Characterization of Plasma Silicon Nitride Layer," Journal of the Electrochemical Society, vol. 130 (Dec. 1983), pp. 2419-2423.
G. M. Samuelson et al., "The Correlations Between Physical and Electrical Properties of PECVD SiN with their Composition Ratios", Journal of the Electrochemical Society, vol. 129 (Aug. 1982), pp. 1773-1778.
U.S. application Ser. No. 303,091 filed Jun. 1989 by Possin et al.

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