Insulator separated vertical CMOS

Details Insulator separated vertical CMOS Insulator separated vertical CMOS

1989-12-26

1991-04-23

Hille, Rolf

357 41, 357 55, 357 234, 357 236, 357 237, H01L 2702, H01L 2906, H01L 2910, H01L 2701

Patent

active

050103865

ABSTRACT:
A complementary semiconductor structure comprises a substrate of a first conductivity type upon which a first channel layer of a second conductivity type is formed. The first source/drain layer of the first conductivity type is formed on the surface of the first channel layer and an insulating layer is formed on the surface of the first source/drain layer. A second source/drain layer of the second conductivity type is formed on the surface of the insulating layer and a second channel layer of said first conductivity is formed on the surface of the second source/drain layer. A third source/drain layer of the second conductivity type is formed on the surface of the second channel layer. Gate circuitry is vertically disposed on an edge perpendicular to the plane and adjacent to the first and second channel layers and insulated therefrom.

REFERENCES:
patent: 4450466 (1984-05-01), Nishizawa et al.
patent: 4740826 (1988-04-01), Chatterjee
patent: 4810906 (1989-03-01), Shah et al.

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