Insulation process for integrated circuits

Details Insulation process for integrated circuits Insulation process for integrated circuits

1981-08-27

1984-06-19

Edlow, Martin H.

357 59, 357 236, 357 235, H01L 2934, H01L 2904, H01L 2978

Patent

active

044555687

ABSTRACT:
Capacitors or dual layer metalization interconnects are formed in an integrated circuit utilizing two layers of polycrystalline silicon (22, 24) separated by a thin insulation region (23). The insulation region formed between the two polycrystalline silicon regions has substantially fewer defects than the insulation regions used in prior art techniques due to the use of a unique process wherein the polycrystalline silicon layer (24) overlying the insulation layer (23) protects the insulation layer from attack during subsequent processing. An improved dielectric strength is provided by forming the insulation region (23) utilizing composite layers of silicon oxide (23a, 23c) and silicon nitride (23b).

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Tasch et al., IEEE Trans on Elect. Devices vol. ED-25, No. 1, Jan. 1978, pp 33-41 "The Hi-C RAM Cell Concept".
Posa J. G., Electronics May 22, 1980, pp. 119-129, "What to Expect Next: A Special Report".

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