Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Low workfunction layer for electron emission
Reexamination Certificate
2001-09-10
2003-09-30
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Low workfunction layer for electron emission
C257S010000, C257S412000
Reexamination Certificate
active
06627913
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is directed generally to integrated circuit magnetic memory devices for storing information and, more particularly, to methods and structures for insulating the devices.
2. Description of the Related Art
The memory integrated circuit most commonly used in computers and computer system components is the dynamic random access memory (DRAM), wherein voltage stored in capacitors represents digital bits of information. Electric power must be supplied to these memories to maintain the information because, without frequent refresh cycles, the stored charge in the capacitors dissipates, and the information is lost. Memories that require constant power are known as volatile memories.
Non-volatile memories do not need frequent refresh cycles to preserve their stored information, so they consume less power than volatile memories. There are many applications where non-volatile memories are preferred or required, such as in cell phones or in control systems of automobiles.
Magnetic random access memories (MRAMs) are non-volatile memories. Digital bits of information are stored as alternative directions of magnetization in a magnetic storage element or cell. The storage elements may be simple, thin ferromagnetic films or more complex layered magnetic thin-film structures, such as tunneling magnetoresistance (TMR) or giant magnetoresistance (GMR) elements.
Memory array structures are formed generally of a first set of parallel conductive lines covered by an insulating layer, over which lies a second set of parallel conductive lines, perpendicular to the first lines. Either of these sets of conductive lines can be the bit lines and the other the word lines. In the simplest configuration, the magnetic storage cells are sandwiched between the bit lines and the word lines at their intersections. More complicated structures with transistor or diode configurations can also be used. When current flows through a bit line or a word line, it generates a magnetic field around the line. The arrays are designed so that each conductive line supplies only part of the field needed to reverse the magnetization of the storage cells. Switching occurs only at those intersections where both word and bit lines are carrying current. Neither line by itself can switch a bit; only those cells addressed by both bit and word lines can be switched. In some arrangements, one or both of a sense line and a bit line cooperates with a word line to flip the bit.
FIG. 1
illustrates, by way of example, the three functional layers of a simple TMR device. TMR devices
10
work by electron tunneling from one magnetic layer to another through a thin barrier layer
12
. The tunneling probability is greatest when the magnetic layers
14
,
16
, on either side of the barrier layer
12
, have parallel magnetizations and least when the magnetizations are anti-parallel. In order for the devices to function properly, these layers must be electrically isolated from one another. Any short-circuiting of the tunnel dielectric layer prevents proper reading of the layers' relative magneto-resistance, which represents the data storage of the device.
Materials used in layers of the TMR devices, especially metals such as nickel, iron and cobalt can diffuse out from the devices and into other functional areas of the integrated circuit, especially during subsequent processing steps at elevated temperatures.
In the prior art, the dielectric layer
20
shown in
FIG. 1
served both as electrical insulation around the magnetic memory devices and as a barrier to outdiffusion of TMR device species. Silicon nitride is the material most often used for this dual purpose. Silicon nitride is a very hard material and tends to make conformal layers. When deposited over the magnetic memory array
10
, the top surface of the silicon nitride
20
is not flat, and a chemical mechanical planarization step is performed before additional processing to form conducting lines that contact the top surfaces of the devices.
The high current density carried by the bit and word lines makes copper conductors desirable for MRAM arrays to reduce the likelihood of electromigration. Copper conducting lines are made usually using a damascene process. A copper conducting line
18
, in contact with the bottom of the TMR devices
10
is shown in the plane of the paper in FIG.
1
. To make conducting lines at the top of the devices, first the silicon nitride layer
20
is deposited over the MRAM array. Trenches (
FIG. 2
) are etched into the silicon nitride layer to make contact with the top surfaces
22
of the TMR devices
10
.
If the mask that defines the trenches is even slightly misaligned, the etching step can cause an overetch along the side of the MRAM device. As shown in
FIG. 2
, when the copper
24
is deposited, it can fill the overetched area as well, making copper regions
26
along the sides of the TMR devices
10
and short-circuiting the devices
10
.
Accordingly, structures for and methods of making MRAM arrays with damascene copper conducting lines with greater design tolerance and which will result in increased yield and reliability for MRAM arrays using TMR devices are needed.
SUMMARY OF THE INVENTION
In accordance in one aspect of the present invention, a memory for an integrated circuit and method of fabricating same are provided. An array of magnetic memory devices, preferably TMR junctions, are configured as individual studs and protrude from a substrate. A layer of insulating spacer material is deposited over the array of magnetic memory devices and a spacer etch is performed to remove the spacer material preferentially from top surfaces of the magnetic memory devices and from substrate surface areas between the magnetic memory devices. Next, a filler dielectric layer is deposited to fill at least regions over the substrate and between the magnetic memory devices.
Preferably, the insulating spacer material is also a barrier to outdiffusion of species from the TMR junctions and may consist of silicon carbide (e.g., BLOk™), low temperature silicon nitride or diamond-like carbon. In another embodiment, the insulating spacer material is also a magnetic material and may comprise magnesium-zinc ferrites or nickel-zinc ferrites.
The material for the filler dielectric layer may comprise spin-on-glass, borophosphosilicate glass, fluorinated silicate glass or hydrogen silsesquioxane glass. Preferably, the filler dielectric layer can be etched selectively relative to the spacer material. Trenches are etched into the filler dielectric layer to make contact to the TMR devices as for a damascene process.
In accordance with another aspect of the invention, an array of magnetic memory cells are provided on a substrate wherein each magnetic memory cell comprises a tunneling magnetoresistance (TMR) structure in a stud configuration, a spacer surrounding the TMR structure and at least two electrodes that make contact to the TMR structure. Regions between and over individual cells are filled with a dielectric material that reflows easily.
In one arrangement, the spacer comprises a low k insulator and is a barrier to diffusion of TMR structure species. In another arrangement, the spacer comprises a material with high magnetic permeability. In some arrangements, regions between individual cells have spacer material between the dielectric layer and the substrate, in addition to filler dielectric thereover.
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Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
Nelms David
Nguyen Thinh
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