Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1992-09-30
1994-05-24
Beck, Shrive
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
4274301, 4274432, B05D 512
Patent
active
053147103
ABSTRACT:
An insulation layer forming method for processing a substrate having a first surface area covered with a photo resist mask pattern and a second surface area uncovered with the photo resist mask pattern to form an SiO2 insulation layer on the second surface area of the substrate. The method comprises the steps of dipping the substrate in an organic solvent having no compatibility with water and photo resist, recirculating the organic solvent under heat to remove water from the substrate, solving an organic silicone compound in the organic solvent, and recirculating the organic solvent having the organic silicone compound under heat to form the SiO2 insulation layer while removing a by-product.
REFERENCES:
Patent Abstracts of Japan, vol. 012, No. 324, (E-653), of Japanese Published Application No. 63-090137 (1988), Sep. 2, 1988.
Patent Abstracts of Japan, vol. 015, No. 153 (P1191), of Japanese Published Application No. 30-24550 (1991) Apr. 17, 1991.
Database WPI, Section Ch, Week 4278, Derwent Publications Ltd, London, G.B., Class A, AN 78-75397, & JP-A-53105377 (Sep. 13, 1978).
Database WPI, Section Ch, Week 4779, Derwent Publication Ltd, London, G.B., Class A, AN 79-85335, & JP-A-54133881 (Oct. 17, 1979).
Beck Shrive
Maiorana David M.
Sony Corporation
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