Insulated power multichip package

Details Insulated power multichip package Insulated power multichip package

2000-02-18

2002-10-29

Martin, David (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S761000, C361S717000, C361S704000, C361S707000, C361S751000, C361S768000, C438S121000, C438S122000, C174S050510, C174S050510, C174S252000, C174S254000, C257S684000

Reexamination Certificate

active

06473310

ABSTRACT:

TECHNICAL FIELD
This invention relates to power semiconductor device packages, and more specifically, to a method of insulating power semiconductor chips from one another in a package by physically separating them within a single multichip package, and the resultant multichip package.
BACKGROUND OF THE INVENTION
Oftentimes more than one silicon wafer, or “chip” is present in an integrated circuit package. For instance, one integrated circuit package may contain a signal processing chip, a function control chip, and an amplifying chip all within the same integrated circuit package. This is especially true as the miniaturization of electronic devices continues, requiring one-package solutions where previously multi-package solutions were acceptable.
Shown in
FIG. 1
a
is a representation of a twenty pin Dual In-Line Package (DIP). Shown is an integrated circuit (IC) package
10
, having twenty pins labeled
12
, ten pins on each side of the IC package
10
.
FIG. 1
b
shows the IC package
10
without a top cover, giving a view of how the pins
12
are connected within the IC package. The IC package
10
contains a chip
20
that has several bonding pads
14
. Each bonding pad
14
is connected to one of the pins
12
of the IC package
10
in a conventional manner, such as by thermosonic or ultrasonic bonding. The chip
20
is coupled to eight of the twenty pins
12
of the IC package
10
. The other twelve pins
12
of the IC package
10
are coupled to the bonding pads
14
of a chip
30
.
The chips
20
and
30
are attached to a common slug
40
, shown in FIG.
2
. Often the common slug
40
is made from a metal material such as copper, but any suitable material can be used. When the common slug
40
is made from copper, the chips
20
and
30
can be directly soldered to, or otherwise physically attached to the slug, such as by eutectic bonding. The common slug
40
provides a stable base for handling during the creation of the IC package
10
. Additionally, the slug acts as a large heat dissipater, removing heat from the chips
20
and
30
developed during their operation.
However, sometimes the regular operation of the individual chips
20
and
30
causes them to interfere with one another during operation. If, for example, the chip
20
produces an electrical signal that interferes with the operation of the chip
30
, the common slug
40
carries that electrical signal directly to the chip
30
, causing the interference. To prevent such interference, an electrical insulating layer
50
(
FIG. 2
) is provided between the chip
30
and the common slug
40
. This electrical insulating layer can be an adhesive tape, for example, or a layer of molding compound.
The presence of this electrical insulating layer
50
degrades the efficient heat transfer between the chip
30
and the common slug
40
. Therefore, the chip
30
, when electrically insulated from the common slug
40
by the electrical insulating layer
50
, runs at a higher temperature than if it were directly soldered to the common slug
40
. This higher temperature can degrade the performance of the chip
30
, or even cause it to malfunction. However, in instances where the electrical insulating layer
50
is necessary, the chip cannot be soldered directly to the common slug
40
otherwise the electrical interference between the chip
20
and chip
30
would be present.
SUMMARY OF THE INVENTION
One embodiment of the invention presents a multichip integrated circuit package having at least two chips electrically isolated from one another. Within the multichip integrated circuit package is a slug that is directly coupled to at least two chips, without any intervening insulating layers. The slug is physically separated at an appropriate place between the two chips, so that electrical interference between the two chips is eliminated.
Another embodiment of the invention presents a method for creating a multichip integrated circuit package having at least two chips electrically isolated from one another. The method begins with directly attaching the two chips to a heat dissipating slug, preferably by soldering the chips to the slug. In one embodiment, the heat dissipating slug has a pre-cut groove running between the chips. Once the chips are attached to the slug, the slug is molded into the multichip integrated circuit package. Then, the slug is physically separated into two pieces from the underside, the separation running along the pre-cut groove. In one embodiment, the slug is cut with a saw.


REFERENCES:
patent: 4561011 (1985-12-01), Kohara et al.
patent: 5297006 (1994-03-01), Mizukoshi
patent: 5317194 (1994-05-01), Sako
patent: 5471366 (1995-11-01), Ozawa
patent: 5780926 (1998-07-01), Seo
patent: 6049074 (2000-04-01), Endo et al.

Affiliated with

Also associated with

Rating

Insulated power multichip package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Insulated power multichip package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Insulated power multichip package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2989679