Insulated high speed semiconductor switching device

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With large area flexible electrodes in press contact with...

Reexamination Certificate

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C257S688000, C257S698000, C257S700000

Reexamination Certificate

active

06707144

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor element housed in an insulated vessel and external terminals for controlling potentials of electrodes of the semiconductor element, and particularly to a gate commuted semiconductor device in which a main current is commuted upon turning-off thereof.
2. Related Art
A GCT thyristor, in a semiconductor device, has been available as a gate commuted turn-off semiconductor element capable of commuting all of a main current to the gate side on turning-off thereof. Generally, the GCT thyristor is connected to a gate drive unit which is a circuit for driving the gate thereof with wires to be used as a GCT unit.
In
FIGS. 8A and 8B
, there is shown a construction of a conventional GCT thyristor. The GCT thyristor, as shown in the figures, is configured such that a semiconductor substrate
3
is disposed between an anode post electrode
1
and a cathode post electrode
2
via buffer members
5
having conductivity. The semiconductor substrate
3
sandwiched between the anode post electrode
1
and the cathode post electrode
2
is housed in an insulative ceramic cylinder
4
. A flange
16
and a cathode cap
18
are disposed at respective openings of the ceramic cylinder
4
. The cathode cap
18
serves as a member for connecting a cathode terminal base of a gate drive unit board with the cathode electrode of the GCT thyristor. On the semiconductor substrate
3
, formed is a semiconductor element that has a gate electrode and is controlled by a gate signal applied to the gate electrode to commutate all of a main current to the gate side on turning-off thereof.
FIG. 9
is a view showing a ring gate
31
a
and a lead
31
b
of the conventional GCT thyristor. A gate signal is transmitted to the semiconductor substrate
3
from outside through the ring gate
31
a
and the lead line
31
b
. The conventional GCT thyristor has a through-hole formed in the ceramic cylinder
4
through which the lead
31
b
passes to outside of the cylinder
4
.
For the GCT thyristor, when an inductance of a wiring connecting the GCT thyristor with the gate drive unit is large, quick commutation on turning-off would be hindered and cause break-down due to local heat generated within the semiconductor substrate. In such a case, there arises problems of increase in control current and reduction of a high speed switching operation.
For the construction shown in
FIG. 9
, it is sufficient to provide plural leads to reduce a wiring inductance. However, By simply attaching plural leads
31
b
to one ring gate
31
a
, the plural leads would be an obstacle to house the ring gate
31
a
within the ceramic cylinder
4
in an assembly process.
A construction shown in
FIG. 10
has been contrived as an example of a GCT thyristor capable of reducing a wiring inductance. The GCT thyristor shown in the figure uses a gate ring
8
as shown in
FIG. 11
that has plural gate terminals formed in a radial pattern around the center of a semiconductor element. Such the shape allows the inductance to be reduced, and a rising rate (diGQ/dt) of a gate reverse current to be increased largely on the turning-off, thereby enabling quick commutation on the turning-off. Thus an increase of a control current and a high speed switching operation can be achieved.
In
FIG. 10
, an anode fin
10
is disposed on the outer side of the anode post electrode
1
, a cathode fin
11
is disposed on the outer side of the cathode cap
18
. These are coupled each other by pressing with force. A gate ring
8
is sandwiched between two separate ceramic cylinders
4
a
and
4
b
, and fixedly attached to these cylinders
4
a
and
4
b
by silver soldering to be supported so as to ensure insulation between the gate and the cathode. Furthermore, the gate ring
8
is crimped to a ring gate
6
which is a gate electrode by an elastic member
7
such as a spring. In a prior art practice, the inductance is reduced in the above construction.
However, using the two separate ceramic cylinders
4
a
and
4
b
as described above results in complexity of processing of the ceramics, and increase of the number of components which then causes difficulty of maintaining accuracy of components, thereby causing higher cost of the components.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problem and it is an object of the present invention to provide a semiconductor device having a semiconductor element housed in an insulated vessel and external terminals for controlling potentials of electrodes of the semiconductor element, that can increase a control current and achieve a high speed switching operation as well as decreasing the costs of components thereof.
A semiconductor device according to the invention, includes a semiconductor element having a gate electrode to which a main current is commuted when the semiconductor element turns off, the semiconductor element being housed in an insulated vessel. The gate commuted semiconductor device includes plural external terminals that are coupled to the gate electrode of the semiconductor element, plural through-holes that are formed in the insulated vessel, and plural leads each passing through the respective through-holes and connected to their respective external terminals. Each lead has its own terminal (electrode) for electrically connecting with the gate electrode. The leads are disposed with an equal pitch.
According to such a semiconductor device, plural external terminals are connected to the gate electrode, and thus a wiring impedance can be reduced. Therefore increase of control current and a high speed switching operation can be achieved. Furthermore, no necessity arises for complex processing for the insulated vessel and the number of constituents associated therewith decreases, thereby enabling reduction in fabrication cost.
In the above semiconductor device, the terminal of the lead may have discoidal shape, and then the terminals of the leads may preferably be stacked to be connected to the gate electrode of the semiconductor element. By using such the terminals to acquire electric connection with the semiconductor element, an effective electrode area can be sufficiently secured for supplying a gate signal from the central section of the semiconductor element.
In the above semiconductor device, the terminal of the lead may have ringed shape, and then the terminals of the leads may preferably be stacked to be connected to the gate electrode of the semiconductor element. By using such the terminals to acquire electric connection with the semiconductor element, supply of a gate signal can be possible from the peripheral section of the semiconductor element.
In the above semiconductor device, the terminal of the lead may have deltaic shape, and then the terminals of the leads may preferably be juxtaposed to be connected to the gate electrode of the semiconductor element. By using such the terminals juxtaposed, a gate signal is supplied almost uniformly to the gate electrode, thereby enabling a more efficient commuting operation to be realized than in a case where the terminals are stacked in use.
In the above semiconductor device, the terminal of the lead may have approximately U-shape, and then the terminals of the leads may preferably be juxtaposed to be connected to the gate electrode of the semiconductor element. By using such the terminals juxtaposed, a gate signal is supplied almost uniformly to the gate electrode when the gate signal is supplied from the peripheral section of the semiconductor element, thereby enabling a more efficient commuting operation to be realized than in a case where the terminals are stacked in use.
In the above semiconductor device, some of all terminals of the leads may have discoidal shape, and the others thereof may have ringed shape. The terminals with discoidal shape may be stacked and connected to the gate electrode of the semiconductor element in the vicinity of a central section of the gate electrode, and the terminals

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