Patent
1987-01-21
1989-04-11
Edlow, Martin H.
357 231, 357 2314, 357 68, 357 41, H01L 2710
Patent
active
048210846
ABSTRACT:
Extension directions of source electrode layer and a drain electrode are parallel to rows or columns of an array of alternately arranged source regions and drain regions, thereby forming widths of source and drain electrode layers wider than those of a conventional transistor to obtain a large mutual conductance.
REFERENCES:
patent: 4015278 (1977-03-01), Fukuta
patent: 4152714 (1979-05-01), Hendrickson et al.
patent: 4603341 (1986-07-01), Bertin et al.
patent: 4636825 (1987-01-01), Baynes
Patent Abstracts of Japan, vol. 9, No. 181, 26th Jul. 1985, JP-A-60 53 085.
Kinugasa Masanori
Ohta Hirokata
Shigehara Hiroshi
Tanaka Fuminari
Edlow Martin H.
Kabushiki Kaisha Toshiba
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