Patent
1983-09-16
1987-04-21
James, Andrew J.
357 41, 357 42, 357 236, 357 22, H01L 2978
Patent
active
046600620
ABSTRACT:
An insulated gate transistor including a semiconductor substrate, high impurity source and drain regions formed above a channel region of low conductivity, a high impurity concentration region having a conductivity type opposite to that of the source region, a gate insulating layer extending into the channel region farther inwardly of the substrate than the source region, and a gate electrode positioned on the gate insulating layer. The gate electrode is made of a material having a high potential barrier with respect to the source region. The insulated gate transistor may be used as a driver transistor in an integrated circuit, as a switching transistor in a dynamic RAM memory cell, static RAM memory cell and in a complementary configuration.
REFERENCES:
patent: 3975752 (1976-08-01), Nicolay
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patent: 4131907 (1978-12-01), Ouyang
patent: 4141022 (1979-02-01), Sigg
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patent: 4295267 (1981-10-01), Harrington
patent: 4316203 (1982-02-01), Tohgei
IEEE Electron Device Letters vol. 3 #2 Feb. 1982, pp. 37-40 357/67S by Chow.
IEEE Transactions on Electron Devices vol. 29 #3 Mar. 82 pp. 368-376 by Ohta.
Solid State Electronics, vol. 19 #2, pp. 159-166 Feb. 76 by Mok, ". . . A V Shaped Channel FET" 35722V.
Nishizawa Jun-ichi
Ohmi Tadahiro
Handotai Kenkyu Shinkokai
James Andrew J.
Prenty Mark
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