Insulated gate thyristor

Details Insulated gate thyristor Insulated gate thyristor

2000-02-24

2001-08-21

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Combined with field effect transistor

C257S137000, C257S152000, C257S168000

Reexamination Certificate

active

06278140

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to an insulated gate thyristor. More specifically, the invention related to an insulated gate thyristor used as a power switching device.
BACKGROUND OF THE INVENTION
Thyristors have been used as indispensable devices for large capacity power switching owing to the low ON-state voltage characteristic. Gate Turn-Off (GTO) thyristors, for example, are widely used in these days in high-voltage large-current range applications. The GTO thyristor, however, has revealed drawbacks as follows: first, the GTO thyristor requires large gate current for turn-off, in other words, the thyristor has a relatively small turn-off gain; and secondly, a large-sized snubber is needed to safely turn off the GTO thyristor. In addition, since the GTO thyristor does not show current saturation in its current-voltage characteristic, a passive component, such as a fuse, must be coupled to the thyristor so as to protect a load from short-circuiting. This greatly impedes the reduction in the size and cost of the whole system.
MOS controlled thyristor (hereinafter abbreviated as MCT) as a voltage-driven type thyristor was proposed by V. A. K. Temple in IEEE IEDM Tech. Dig., 1984, p282. Since then, the characteristics of this type of thyristor have been analyzed and improved in various institutions worldwide. This is because the MCT, which is a voltage-driven type device, requires a far simpler gate circuit than the GTO thyristor, while assuring a relatively low ON-state voltage characteristic. The MCT, however, does not show a current saturation characteristic as in the case of the GTO thyristor, and therefore requires a passive component, such as a fuse, in its practical use.
Dr. Pattanayak and others revealed than an emitter switched thyristor (hereinafter abbreviated as EST) shows a current saturation characteristic, as disclosed in U.S. Pat. No. 4,847,671 (Jul. 11, 1989). Subsequently, M. S. Shekar and others proved by actual measurements that a dual channel type emitter switched thyristor (EST-1) shows a current saturation characteristic even in a high voltage range, as disclosed in IEEE Electron Device Letters vol. 12 (1991), p387. In Proceedings of IEEE ISPSD '93, p71 and Proceedings of IEEE ISPSD '94, p195, the inventors of the present invention disclosed results of their analysis on a forward bias safe operation area (FBSOA) and a reverse bias safe operation area (RBSOA) of this EST, and paved the way to the development of a voltage-driven type thyristor having the safe operation area in which the device operates safely when a load is short-circuited.
FIG. 39
shows the structure of this EST device.
In the device as shown in
FIG. 39
, a first p base region
4
, p
30
well region
5
and a second p base region
6
are formed in surface layer of an n base layer
3
deposited on a p emitter layer
1
via an n
+
buffer layer
2
. The p
+
well region
5
forms a part of the first p base layer
4
, and has a relatively large diffusion depth. An n source region
7
is formed in a surface layer of the first p base region
4
, and an n emitter layer
8
is formed in a surface layer of the second p base region
6
. A gate electrode
10
is formed on a gate oxide film
9
over a portion of the first p base region
4
that is interposed between the n source region
7
and an exposed portion of the n base layer
3
, and a portion of the second p base region
6
that is interposed between the n emitter region
8
and the exposed portion of the n base layer
3
. Each of the n source region
7
, n emitter region
8
and the gate electrode
10
has a limited length in the Z-direction in
FIG. 39
, and the first p base region
4
and the second p base region
6
are coupled to each other outside these regions
7
,
8
and electrode
10
. Further, L-shaped p
+
well region
5
is formed outside the coupled portion of the first and second p base regions
4
,
6
. A cathode electrode
11
is formed in contact with both the surface of the p
+
well region
5
, and the surface of the n source region
7
. On the other hand, an anode electrode
12
is formed over the entire area of the rear surface of the p emitter layer
1
.
When the cathode electrode
11
of this device is grounded, and positive voltage is applied to the gate electrode
10
while positive voltage is applied to the anode electrode
12
, an inversion layer (partial accumulation layer) is formed under the gate oxide film
9
, and a lateral MOSFET is thus turned on. As a result, electrons are supplied from the cathode electrode
11
to the n base layer
3
, through the n source region
7
, and the inversion layer (channel) formed in the surface layer of the first p base region
4
. These electrons function as base current for a pnp transistor which consists of the p emitter layer
1
, n
+
buffer layer
2
and n base layer
3
, and the first and second p base regions
4
,
6
and p
+
well region
5
. This pnp transistor operates with this base current. Then, holes are injected from the p emitter layer
1
, and flow into the first p base region
4
through the n
+
buffer layer
2
and n base layer
3
. A part of the holes flow into the second p base region
6
, and then flow under the n emitter region
8
in the Z direction to the cathode electrode
11
. Thus, the device operates in an IGBT (insulated gate bipolar transistor) mode. With a further increase in the current, the pn junction between the n emitter region
8
and the second p base region
6
is forward biased, and a thyristor portion consisting of the p emitter layer
1
, n
+
buffer layer
2
, n base layer
3
, second p base region
6
and n emitter region
8
latches up. In this case, the device operates in a thyristor mode. To turn off the EST, the MOSFET is turned off by lowering the potential of the gate electrode
10
below the threshold of the lateral MOSFET. As a result, the n emitter region
8
is potentially separated from the cathode electrode
11
, and the device stops operating in the thyristor mode.
FIGS. 40 and 41
are cross sectional views of improved ESTs as disclosed in U.S. Pat. No. 5,317,171 issued May 31, 1994 and U.S. Pat. No. 5,319,222 issued Jun. 7, 1994 to M. S. Shekar et al. The improved EST of
FIG. 41
, in particular, is different from the EST shown in
FIG. 39
, and is designed so as to provide a further lowered ON-state voltage characteristic.
FIG. 42
is a cross-sectional view of a FET controlled thyristor as disclosed in U.S. Pat. No. 4,502,070 issued Feb. 26, 1985 to L. Leipold et al. This thyristor is characterized in that the electrode is not in contact with the second p base region
6
.
As is understood from the above description, the EST as shown in
FIG. 39
utilizes the holes flowing in the second p base region
6
in the Z direction so as to forward bias the pn junction between the second p base region
6
and the n emitter region
8
, and therefore a degree of strength of the forward bias decreases in the Z direction toward a contact area of the second p base region
6
with the cathode electrode
11
. Namely, the amount of electrons injected from the n emitter region
8
is not uniform over the length of the pn junction in the Z direction. If this EST is switched from this ON state to the OFF state, a weakly biased portion of the pn junction near the contact area with the cathode electrode
11
initially resumes its reverse-blocking ability, and a deeply biased portion of the pn junction remote from the contact area with the cathode electrode
11
slowly resumes the same ability. This tends to cause current localization or concentration upon turn-off, resulting in lowered capability to withstand breakdown of the EST during turn-off.
Although the EST shown in
FIG. 40
operates in a similar manner to the EST of
FIG. 39
, the EST of
FIG. 40
can be turned off more quickly since the cathode electrode
11
extends in the Y direction, to be in direct contact with the surface of the second p base region
6
. Further, the EST of
FIG. 40
show

Affiliated with

Also associated with

Rating

Insulated gate thyristor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Insulated gate thyristor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Insulated gate thyristor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2538235