Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-10-18
2003-11-04
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S330000, C257S331000, C257S332000
Reexamination Certificate
active
06642600
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an insulated gate semiconductor device having a trench gate structure, and more particularly to a gate interconnection structure of the same device.
2. Description of the Background Art
An insulated gate semiconductor device having a trench gate structure is generally referred to as a vertical MOS transistor (as a UMOS from the shape of trenches). Since the vertical MOS transistor, having gate electrodes formed in a vertical direction unlike a lateral MOS transistor having planar gates, needs a smaller area for one cell, it allows an increase in the number of cells per unit area through micromachining. The increase in the number of cells per unit area (density) enlarges a channel area, allowing a larger amount of currents to flow in an ON state. The resistance of the UMOS transistor in this case is referred to as “ON-resistance (Ron)”, which is a key item of characteristics of a device. Contrastively in the lateral MOS transistor, there is a limitation in reduction of ON-resistance Ron since increasing the cell density leads to an increase in j-FET resistance. For effective use of such a characteristic feature of the UMOS transistor, the gate trench structure is mainly adopted in power devices such as MOSFETs (MOS Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors).
Before pointing out problems to be solved in the present invention, first taken is an overview of a gate interconnection structure of a UMOSFET (no prior art) which is a unpublished product made by the present applicant company. In this unknown structure, a gate control electrode buried inside a trench which penetrates a p-type base layer is drawn up to above a surface of the trench at a cell end portion of the UMOSFET and the drawn-up portion of the gate control electrode is electrically connected to a gate electrode connected to a gate pad through a gate contact portion.
Next, discussion will be presented on a gate reliability test for the UMOSFET, relating to a main problem to be solved in the present invention. Further, a general HTGB test (high temperature gate bias test) will be herein discussed.
First, a UMOSFET is kept at a high temperature by using a constant temperature bath or a hot plate. In this state, a drain electrode and a source electrode are short-circuited by an external interconnection and a gate voltage VGS is applied across a gate electrode and the source electrode. At this time, tests are executed in both cases where the polarity of the gate voltage is positive and where it is negative. Further, with the gate voltage VGS set to a value close to a gate assured-proficiency voltage in a UMOSFET, the test is executed. Then, under this state, with the temperature of the UMOSFET kept constant, the gate voltage VGS is applied for a long time to check deterioration of a gate oxide film and the degree of variations in other characteristics.
In this case, at a corner portion of the trench, an electric field equivalent to the gate voltage VGS occurs against the gate oxide film formed on an inner wall of the trench, like in an ON-operation state. The electric field stress against the gate oxide film at the corner portion is much stronger than that in the ON-operation because of (1) high temperature atmosphere, (2) the value of the gate voltage VGS higher than that in the normal ON-operation and (3) a long-time continuous energization. Therefore, the HTGB test is means for acceleratedly checking the proficiency in withstand insulation voltage of the gate oxide film, and can be used for determinating an original lifetime of the gate oxide film.
In the product UMOSFET having the above gate interconnection structure, an electric field stress is applied to the whole surface of the gate oxide film through the HTGB test, and especially, a much stronger electric field stress is applied to the corner portion of the outermost trench. The reason are (1) that at the portion of the outermost trench, a silicon substrate is opened in a form almost square in order to draw the gate control electrode up to above the trench and the gate oxide film formed along a surface of the silicon substrate having a square bent portion has a film thickness much thinner at the square portion than that of other portions since the oxidation speed decreases at the square portion of the silicon substrate, and (2) that the withstand insulation voltage is lower at the portion of the outermost trench than a flat portion of the oxide film since the gate oxide film has a shape with a relatively large curvature at the portion of the outermost trench and much stronger electric field stress is applied to the gate oxide film at the portion of the outermost trench than that applied to other portions.
The following methods are possible to solve the above problem.
1) A method to make an oxide film at the corner portion thicker than those formed on the inner wall of the trench and the flat portion by implanting As (arsenic) as an n
+
-type impurity into the portion of the outermost trench, utilizing a phenomenon that the oxidation speed increases in a region in which n
+
-type impurities are implanted when a gate oxide film is formed by a heat treatment (no prior art).
2) A method to relieve the electric field stress by providing a round at the corner portion through an isotropic silicon etching which is performed immediately after the formation of the trench (no prior art).
3) A method to relieve the electric field stress by making the shape of the oxide film gentler through optimization of process conditions (heat history, gas atmosphere) in the formation of the gate oxide film (no prior art).
The method (1), however, produces an effect in a device which allows a long-time heat treatment, in other words, a device having a gate oxide film which is thick to some degree but can not produce a sufficient effect in a device which does not allow a long-time heat treatment, in other words, a device having a gate oxide film which is relatively thin.
Further, the method (2) raises a problem that the manufacturing process becomes complicate since an etching process is necessarily added. Moreover, in the method (2), the width of the trench becomes larger since the whole of trench is also etched at the same time, and this causes deterioration in yield because of short design margin and also causes a decrease in channel width in a transistor cell having a mesh structure, resulting in an increase in ON-resistance.
Furthermore, in the method (3), similarly in the method (2), since the gate oxide film has a round shape to some degree at the corner portion, it is possible to relieve the electric field stress to some degree but the withstand insulation voltage of the gate oxide film at the corner portion is nowhere near that of the gate oxide film at the flat portion because the film thickness of the gate oxide film at the corner portion does not become thicker. Therefore, the method (3) is not a radical solution.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide an insulated gate semiconductor device which ensures an improvement in yield through enhancing a withstand insulation voltage and reliability of gates.
It is a second object of the present invention to improve a main breakdown voltage between the first and second main electrodes in the insulated gate semiconductor device.
It is a third object of the present invention to reduce a gate wire resistance.
It is a fourth object of the present invention to reduce the number of process steps in a method of manufacturing such an insulated gate semiconductor device.
The present invention is intended for an insulated gate semiconductor device having an MOS transistor structure.
According to a first aspect of the present invention, the insulated gate semiconductor device having an MOS transistor structure includes a semiconductor substrate of a first conductivity type having a first main surface and a second main surface which are opposed to each other in a third direction, a
Narazaki Atsushi
Uryuu Katsumi
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Wojciechowicz Edward
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