Active solid-state devices (e.g. – transistors – solid-state diode – With specified impurity concentration gradient – Stepped profile
Patent
1994-09-07
1996-04-23
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
With specified impurity concentration gradient
Stepped profile
257335, 257365, 257389, 257395, 257404, 257900, H01L 2936, H01L 29167
Patent
active
055106480
ABSTRACT:
An insulated gate semiconductor device (10) having a pseudo-stepped channel region (20B) between two P-N junctions (21B and 22B). The pseudo-stepped channel region (20B) is comprised of an enhancement mode portion (26B) and a depletion mode portion (28B), the enhancement mode portion (26B) being more heavily doped than the depletion mode portion (28B). One P-N junction (21B) is formed at an interface between a source region (18B) and the enhancement mode portion (26B). The enhancement mode portion (26B) has a substantially constant doping profile, thus slight variations in the placement of the source region (18B) within the enhancement region (26B) do not result in significant variations in the threshold voltage of the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) is well suited for the design of low voltage circuits because of the small variations of the threshold voltage.
REFERENCES:
patent: 4949136 (1990-08-01), Jain
patent: 5170232 (1992-12-01), Narita
patent: 5371394 (1994-12-01), Ma et al.
Buxo Juan
Davies Robert B.
Zdebel Peter J.
Crane Sara W.
Dover Rennie William
Motorola Inc.
Tang Alice W.
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