Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2000-05-30
2001-11-27
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S124000, C257S330000, C257S341000
Reexamination Certificate
active
06323508
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an insulated gate semiconductor device having trench•gate and a manufacturing method thereof.
2. Description of the Background Art
The insulated gate semiconductor device is a semiconductor device having the structure in which p-type and n-type semiconductor layers are alternately joined, main electrodes through which main current flows are electrically connected to the semiconductor layers on both ends, and a gate electrode for forming a channel by applying the electric field is connected to at least one of the semiconductor layers with an insulating film interposed therebetween. In this insulated gate semiconductor device, the current flowing between the two main electrodes, i.e., the main current, is controlled by the voltage applied to the gate electrode. Typical examples thereof include the MOS transistors and the insulated gate bipolar transistors (simply referred to as IGBT).
The IGBTs for electric power generally have the structure in which a large number of IGBT elements (referred to as unit cells, hereinafter) are connected in parallel. It is the same in the MOS transistors for electric power, too. Especially, the insulated gate semiconductor devices having trench•gate, that is, the devices having the structure in which the gate electrode is buried in the trench formed in the upper surface of the semiconductor substrate have attracted special interest as excellent devices having such advantages as being capable of enhancing the integration degree because of easy miniaturization and simple producing processes. Two examples of the conventional insulated gate semiconductor devices having the trench•gate will now be described below.
<First Conventional Example>
First, the MOS transistor having trench gate (referred to as UMOS hereinafter) disclosed in U.S. Pat. No. 4,767,722 is considered.
FIG. 40
is a front section view of this device. A section of one unit cell is shown in FIG.
40
. In this UMOS
40
, an N
−
-type semiconductor layer
4
containing N-type impurity of a low concentration is formed on a semiconductor substrate constituting an N
+
-type semiconductor layer
1
containing N-type impurity of a high concentration, and a P base layer
5
is formed by diffusing P-type impurity on the N
−
semiconductor layer
4
. Furthermore, on the upper main surface of the P base layer
5
, an N
+
emitter layer
6
is selectively formed by selectively diffusing N-type impurity of a high concentration. These four semiconductor layers constitute a flat board like semiconductor base body
20
. A trench
7
is formed in the upper main surface of the semiconductor base body
20
from the exposed part of the N
+
emitter layer
6
toward the deeper portion. This trench
7
passes through the N
+
emitter layer
6
and the P base layer
5
to reach the N
−
semiconductor layer
4
. Accordingly, the side surface of the trench
7
is adjacent to the N
+
emitter layer
6
, the P base layer
5
and the upper surface portion of the N
−
semiconductor layer
4
.
A gate insulating film
9
is formed on the inner wall surface of the trench
7
, and a gate electrode
10
composed of polysilicon is buried inside the gate insulating film
9
. Accordingly, the gate electrode
10
faces the N
+
emitter layer
6
, the P base layer
5
and the upper surface portion of the N
−
semiconductor layer
4
with the gate insulating film
9
interposed therebetween. The voltage is applied to the gate electrode
10
and then an N channel is formed in the P base layer
5
. That is, the region of the P base layer
5
facing the gate electrode
10
serves as a channel region
8
. A drain electrode
13
is formed on the lower main surface of the semiconductor base body
20
, i.e., on the lower main surface of the N
+
semiconductor layer
1
. A source electrode
12
is formed over part of the exposed N
+
emitter layer
6
and the exposed P base layer
5
in the upper main surface of the semiconductor base body
20
.
FIG. 41
is a plan view of the UMOS
40
shown in FIG.
40
. The upper main surface of the UMOS
40
with the source electrode
12
removed therefrom, i.e., the upper main surface of the semiconductor base body
20
is shown in FIG.
41
. As shown in
FIG. 41
, the gate electrode
10
is formed in a lattice-like form, and the N
+
emitter layer
6
is exposed in the upper main surface of the semiconductor base body
20
in the form like rectangular rings adjacent to the rectangular gate electrode
10
. Further, the P base layer
5
is exposed on the upper main surface of the semiconductor base body
20
in the rectangular areas surrounded by the ring-like N
+
emitter layer
6
. In
FIG. 41
, the outlines of the regions in which the source electrode
12
is in contact with the upper main surface of the semiconductor base body
20
are represented by the dotted lines. That is, the source electrode
12
is electrically connected to the entire surface of the P base layer
5
exposed in the rectangular regions and part of the N
+
emitter layer
6
adjacent to the periphery thereof.
When using this UMOS
40
, the external power source is first connected to apply a drain voltage V
DS
in the positive direction between the drain electrode
13
and the source electrode
12
. In this condition, a gate voltage V
GS
exceeding a predetermined gate threshold voltage V
GS(th)
is applied in the positive direction between the gate electrode
10
and the source electrode
12
(i.e., the gate is turned on), and then the P-type channel region
8
which is a part of the P-type P base layer
5
is inverted to the N-type to form an N-type channel in the channel region
8
. This channel implements a conductive state between the p base layer
5
and the N
−
semiconductor layer
4
. As a result, the main current flows from the drain electrode
13
to the source electrode
12
. That is, the UMOS
40
goes into the conductive state. The resistance between the drain electrode
13
and the source electrode
12
at this time is called ON resistance R
ON
. It is desirable that the ON resistance R
ON
is as low as possible to decrease the loss when the UMOS
40
becomes conductive.
Next, when the gate voltage V
GS
is returned to a value of zero or minus (backward bias), (that is, the gate is turned off), the channel formed in the channel region
8
disappears and the channel region
8
returns to the original P-type conductivity form. As a result, it is cut off between the P base layer
5
and N
−
semiconductor layer
4
, so that the main current does not flow. That is to say, the UMOS
40
becomes non-conductive.
<Second Conventional Example>
Next, another example of conventional device is considered.
FIG. 42
is a fragmentary cross-section perspective view of the IGBT (referred to as UMOS-IGBT hereinafter) having trench gate disclosed in U.S. Pat. No. 4,994,871. Three unit cells are shown in FIG.
42
. In this UMOS-IGBT
80
, an N
+
buffer layer
63
containing N-type impurity of a high concentration is formed on a semiconductor substrate constituting a P
+
collector layer
62
containing P-type impurity of a high concentration, and an N
−
semiconductor layer
64
containing N-type impurity of a low concentration is formed on the N
+
buffer layer
63
. On the N
−
semiconductor layer
64
, a P base layer
65
is formed by diffusing P-type impurity, and on the upper main surface of the P base layer
65
, an N
+
emitter layer
66
is formed in a stripe form by selectively diffusing N-type impurity of a high concentration. That is, the N
+
emitter layer
66
and the P base layer
65
are exposed on the upper main surface of the semiconductor base body
60
alternately in the stripe form. These five semiconductor layers form the flat board like semiconductor base body
60
.
Trenches
67
are formed on the upper main surface of this semiconductor base body
60
. The t
Harada Masana
Minato Tadaharu
Nishihara Hidenori
Takahashi Hideki
Flynn Nathan
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Sefer Ahmed N.
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