Insulated gate semiconductor device

Details Insulated gate semiconductor device Insulated gate semiconductor device

2007-05-01

2007-05-01

Baumeister, B. William (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

With switching speed enhancement means

C257S331000, C257SE29201

Reexamination Certificate

active

11076889

ABSTRACT:
A CSTBT includes a carrier stored layer (113) formed between a P base region (104) and a semiconductor substrate (103) and the carrier stored layer has an impurity concentration higher than that of the semiconductor substrate (103). The P base region (104) in a periphery of a gate electrode (110) functions as a channel. When it is assumed that an impurity concentration of a first carrier stored layer region (113a) just under the channel is ND1and an impurity concentration of a second carrier stored layer region (113b) other than just under the channel is ND2in the carrier stored layer (113), the relationship of the impurity concentrations is defined by ND1<ND2.Thus, a gate capacity and a short-circuit current can be controlled and variation in threshold voltage can be prevented.

REFERENCES:
patent: 6781200 (2004-08-01), Ishimura et al.
patent: 2003-224278 (2003-08-01), None

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