Patent
1977-11-21
1979-10-23
Clawson, Jr., Joseph E.
357 51, 357 53, 357 54, 357 89, 357 91, H01L 2978
Patent
active
041722604
ABSTRACT:
In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, said high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode extends over and beyond said gate electrode and said high resistance region through said insulating film and terminates over said intermediate region.
REFERENCES:
P. Krick et al., "Integratable, Symmetrical, High-Voltage MOSFET Structure", IBM Tech. Discl. Bull., vol. 15 #6, Nov. 1972, pp. 1184, 1185.
I. Yoshida et al., "Device Design of an Ion-Implanted High Voltage MOSFET, " J. Jap. Soc. of Appl. Phys., vol. 44, 1975, pp. 249-255.
Furumi Masatomo
Itoh Hidefumi
Katsueda Mineo
Ochi Shikayuki
Okabe Takeaki
Clawson Jr. Joseph E.
Hitachi , Ltd.
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