Insulated gate field effect transistor with high breakdown volta

Details Insulated gate field effect transistor with high breakdown volta Insulated gate field effect transistor with high breakdown volta

1990-09-17

1992-09-01

Hille, Rolf

357 233, 357 238, 357 38, H01L 2910, H01L 2968, H01L 2974

Patent

active

051443899

ABSTRACT:
An MIS FET has an off-set gate structure in which a gate electrode and a drain region. The drain region is formed of an n type impurity region of a high concentration and has a pn junction region provided between the drain region and the p type silicon substrate. Further, n type impurity regions of the low concentration are in contact with a part of a peripheral portion of the n type impurity regions of the high concentration. The n type impurity regions of the low concentration alleviate the concentration of the electric field near the drain region to increase the drain breakdown voltage. The pn junction region of the n type impurity region of the high concentration and the p type silicon substrate increases a junction capacitance of the entire drain region, increases a surge current discharged to the substrate side from the drain region for the surge breakdown to increase the surge withstanding amount.

REFERENCES:
patent: 4893157 (1990-01-01), Miyazawa et al.
patent: 4980743 (1990-12-01), Nakagawa et al.

Affiliated with

Also associated with

Rating

Insulated gate field effect transistor with high breakdown volta does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Insulated gate field effect transistor with high breakdown volta, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Insulated gate field effect transistor with high breakdown volta will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-771488