Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-12-21
2004-06-22
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S063000, C365S071000
Reexamination Certificate
active
06754104
ABSTRACT:
The present application is also related to the following applications, all of which are filed simultaneously herewith, and which are hereby incorporated by reference as if fully set forth herein:
An application Ser. No. 10/029,077 entitled “MEMORY CELL UTILIZING NEGATIVE DIFFERENTIAL RESISTANCE FIELD-EFFECT TRANSISTORS”; and
An application Ser. No. 10/028,394 entitled “DUAL MODE FET & LOGIC CIRCUIT HAVING NEGATIVE DIFFERENTIAL RESISTANCE MODE”;
An application Ser. No. 10/028,089 entitled “CHARGE PUMP FOR NEGATIVE DIFFERENTIAL RESISTANCE TRANSISTOR”;
An application Ser. No. 10/028,085 entitled “IMPROVED NEGATIVE DIFFERENTIAL RESISTANCE FIELD EFFECT TRANSISTOR (NDR-FET) & CIRCUITS USING THE SAME”.
FIELD OF THE INVENTION
This invention provides a semiconductor device, having a variety of applications such as a bistable latch or a logic circuit, in which one or more insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field-effect transistor elements are combined and formed on a common substrate. The present invention is applicable to a wide range of semiconductor integrated circuits, particularly for high-density memory and logic applications.
BACKGROUND OF THE INVENTION
Devices that exhibit a negative differential resistance (NDR) characteristic, such that two stable voltage states exist for a given current level, have long been sought after in the history of semiconductor devices. A new type of CMOS compatible, NDR capable FET is described in the aforementioned applications to King et al. referenced above. The advantages of such device are well set out in such materials, and are not repeated here.
NDR devices and their applications are further discussed in a number of references, including the following that are hereby incorporated by reference and identified by bracketed numbers [ ] where appropriate below:
[1] P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun and G. I. Haddad, “Digital Circuit Applications of Resonant Tunneling Devices,”
Proceedings of the IEEE
, Vol. 86, No. 4, pp. 664-686, 1998.
[2] W. Takao, U.S. Pat. No. 5,773,996, “Multiple-valued logic circuit” (issued Jun. 30, 1998)
[3] Y. Nakasha and Y. Watanabe, U.S. Pat. No. 5,390,145, “Resonance tunnel diode memory” (issued Feb. 14, 1995)
[4] J. P. A. Van Der Wagt, “Tunneling-Based SRAM,”
Proceedings of the IEEE
, Vol. 87, No. 4, pp. 571-595, 1999.
[5] R. H. Mathews, J. P. Sage, T. C. L. G. Sollner, S. D. Calawa, C. -L. Chen, L. J. Mahoney, P. A. Maki and K. M Molvar, “A New RTD-FET Logic Farnily,”
Proceedings of the IEEE
, Vol. 87, No. 4, pp. 596-605, 1999.
[6] H. J. De Los Santos, U.S. Pat. No. 5,883,549, “Bipolar junction transistor (BJT)-resonant tunneling diode (RTD) oscillator circuit and method (issued Mar. 16, 1999)
[7] S. L. Rommel, T. E. Dillon, M. W. Dashiell, H. Feng, J. Kolodzey, P. R. Berger, P. E. Thompson, K. D. Hobart, R. Lake, A. C. Seabaugh, G. Klimeck and D. K. Blanks, “Room temperature operation of epitaxially grown Si/Si
0.5
Ge
0.5
/Si resonant interband tunneling diodes,”
Applied Physics Letters
, Vol. 73, No. 15, pp. 2191-2193, 1998.
[8] S. J. Koester, K. Ismail, K. Y. Lee and J. O. Chu, “Negative differential conductance in lateral double-barrier transistors fabricated in strained Si quantum wells,”
Applied Physics Letters
, Vol. 70, No. 18, pp. 2422-2424, 1997.
[9] G. I. Haddad, U. K. Reddy, J. P. Sun and R. K. Mains, “The bound-state resonant tunneling transistor (BSRTT): Fabrication, d.c. I-V characteristics, and high-frequency properties,”
Superlattices and Microstructurer
, Vol. 7, No. 4, p. 369, 1990.
[10] Kulkarni et. al., U.S. Pat. No. 5,903,170, “Digital Logic Design Using Negative Differential Resistance Diodes and Field-Effect Transistors (issued May 11, 1999).
A wide range of circuit applications for NDR devices are proposed in the above references, including multiple-valued logic circuits [1,2], static memory (SRAM) cells [3,4], latches [5], and oscillators [6]. To date, technological obstacles have hindered the widespread use of NDR devices in conventional silicon-based integrated circuits (ICs). The most significant obstacle to large-scale commercialization has been the technological challenge of integrating high-performance NDR devices into a conventional IC fabrication process. The majority of NDR-based circuits require the use of transistors, so the monolithic integration of NDR devices with predominant complementary metal-oxide-semiconductor (CMOS) transistors is the ultimate goal for boosting circuit functionality and/or speed. Clearly, the development of a CMOS-compatible NDR device technology would constitute a break-through advancement in silicon-based IC technology. The integration of NDR devices with CMOS devices would provide a number of benefits including at least the following for logic and memory circuits:
1) reduced circuit complexity for implementing a given function;
2) lower-power operation; and
3) higher-speed operation.
Significant manufacturing cost savings could be achieved concomitantly, because more chips could be fabricated on a single silicon wafer without a significant increase in wafer-processing cost.
A tremendous amount of effort has been expended over the past several decades to research and develop silicon-based NDR devices in order to achieve compatibility with mainstream CMOS technology, because of the promise such devices hold for increasing IC performance and functionality. Efforts thus far have yielded NDR devices that require either prohibitively expensive process technology or extremely low operating temperatures which are impractical for high-volume applications. One such example in the prior art requires deposition of alternating layers of silicon and silicon-germanium alloy materials using molecular beam epitaxy (MBE) to achieve monolayer precision to fabricate the NDR device [7]. MBE is an expensive process which cannot be practically employed for high-volume production of semiconductor devices. Another example in the prior art requires the operation of a device at extremely low temperatures (1.4K) in order to achieve significant NDR characteristics [8]. This is impractical to implement for high-volume consumer electronics applications.
Three (or more) terminal devices are preferred as switching devices, because they allow for the conductivity between two terminals to be controlled by a voltage or current applied to a third terminal, an attractive feature for circuit design as it allows an extra degree of freedom and control in circuit designs. Three-terminal quantum devices which exhibit NDR characteristics such as the resonant tunneling transistor (RTT) [9] have been demonstrated; the performance of these devices has also been limited due to difficulties in fabrication, however. Some bipolar devices (such as SCRs) also can exhibit an NDR effect, but this is limited to embodiments where the effect is achieved with two different current levels. In other words, the current-vs.-voltage (I-V) curve of this type of device is not as useful because it does not provide two stable voltage states for a given current.
Accordingly, there exists a significant need for the monolithic integration of three-terminal NDR devices with conventional field-effect transistors by means of a single fabrication process flow.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a semiconductor device having a variety of applications such as bistable latch or logic circuits through the combination of one or more insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance field-effect transistor (NDR-FET) elements.
A second object of the present invention is to provide a practical method of manufacturing a semiconductor device utilizing a single fabrication process flow, so that an IGFET and an NDR-FET can be formed on a common substrate.
For achie
Gross J. Nicholas
Nguyen Tuan T.
Progressant Technologies, Inc.
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