Insulated gate field effect transistor and method for fabricatin

Details Insulated gate field effect transistor and method for fabricatin Insulated gate field effect transistor and method for fabricatin

1994-04-04

1995-06-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 45, 437 57, H01L 21265

Patent

active

054279640

ABSTRACT:
Insulated gate field effect transistors (10, 70) having independent process steps for setting lateral and vertical dopant profiles for source and drain regions. In a unilateral transistor (10) , portions (48, 50, 51, 55) of the source region are contained within a halo region (34, 41) whereas portions (49, 47, 52, 64) of the drain region are non contained within a halo region. The source region (60, 65) has a first portion (48, 51) for setting a channel length and a second portion (50, 55 ) for setting a breakdown voltage and a source/drain capacitance. The second portion (50, 55) extends further into the halo region than the first portion (48, 51). In a bilateral transistor (70), portions (84, 89, 90, 91) of the drain region (72, 87) are contained within halo region (75, 79 ).

REFERENCES:
patent: 4062699 (1977-12-01), Armstrong
patent: 4898835 (1990-02-01), Cawlfield
patent: 4949136 (1990-08-01), Jian
patent: 4968639 (1990-11-01), Bergonzoni
patent: 5147811 (1992-09-01), Sakagami
patent: 5162884 (1992-11-01), Liou et al.
patent: 5166087 (1992-11-01), Kakimoto et al.
patent: 5171700 (1992-12-01), Zamanian
patent: 5182619 (1993-01-01), Pfiester
patent: 5202276 (1993-04-01), Malhi
patent: 5248627 (1993-09-01), Williams
patent: 5258635 (1993-11-01), Nitayama et al.
patent: 5270235 (1993-12-01), Ito
C. F. Codella et al., "Submicron IGFET Device with Double Implanted Lightly Doped Drain/Source Structure", IBM Technical Disclosure Bulletin, vol. 26, No. 12, May 1984, pp. 6584-6586.
H. Yoshimura et al., "New CMOS Shallow Junction Well FET Structure (CMOS-SJET) for Low Power-Supply Voltage", IEEE, pp. 909-912 (Apr., 1992).

Affiliated with

Also associated with

Rating

Insulated gate field effect transistor and method for fabricatin does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Insulated gate field effect transistor and method for fabricatin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Insulated gate field effect transistor and method for fabricatin will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-286942