Insulated gate FET having a buried insulating barrier

Details Insulated gate FET having a buried insulating barrier Insulated gate FET having a buried insulating barrier

1987-08-25

1989-12-05

Wojciechowicz, Edward J.

357 233, 357 234, 357 237, 357 238, 357 2312, H01L 2978

Patent

active

048856185

ABSTRACT:
A metal-oxide semiconductor field-effect transistor (MOSFET) device having an insulating barrier buried in the substrate between the device's source and drain regions. The insulating barrier can be in contact with the source region of the MOS device. The barrier is implanted in the substrate through a masked implantation of high doses of oxygen, followed by an annealing of the oxygen to form the silicon dioxide insulating barrier. The insulating barrier can be either discrete or part of a continuous sheet of silicon dioxide placed below the silicon substrate. Placing the insulating barrier between the source and drain regions substantially diminishes the punch-through effect of subsurface currents, thereby increasing the punch-through voltage. This permits the construction of MOS devices having shorter channel lengths with resulting higher circuit density and greater speed.

REFERENCES:
patent: 4523213 (1985-06-01), Konaka et al.
patent: 4571606 (1986-02-01), Benjamin et al.

Affiliated with

Also associated with

Rating

Insulated gate FET having a buried insulating barrier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Insulated gate FET having a buried insulating barrier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Insulated gate FET having a buried insulating barrier will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2037478