Insulated gate e-mode transistors

Details Insulated gate e-mode transistors Insulated gate e-mode transistors

2008-11-26

2010-12-14

Purvis, Sue (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

C257S201000, C257SE27061, C257SE29194, C257SE21409, C438S285000

Reexamination Certificate

active

07851825

ABSTRACT:
Enhancement-mode III-nitride transistors are described that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described. The devices can include a charge depleting layer under the gate and/or a charge enhancing layer outside of the gate region, that is, in the access region.

REFERENCES:
patent: 7268375 (2007-09-01), Shur et al.
patent: 2006/0157729 (2006-07-01), Ueno et al.
patent: 2007/0158692 (2007-07-01), Nakayama et al.
patent: 2007/0205433 (2007-09-01), Parikh et al.
patent: 2008/0237640 (2008-10-01), Mishra et al.
patent: 2009/0072272 (2009-03-01), Suh et al.
patent: 2009/0085065 (2009-04-01), Mishra et al.
Stacia Keller et al., “Method for Heteroepitaxial Growth of High-Quality N-Face GaN, InN, and AIN and their Alloys by Metal Organic Chemical Vapor Deposition”, U.S. Appl. No. 60/866,035, filed Nov. 15, 2006, 30 pp.
Umesh Mishra et al., “N-Face High Electron Mobility Transistors with Lower Buffer Leakage and Low Parasitic Resistance”, U.S. Appl. No. 60/908,914, filed Mar. 29, 2007, 20 pp.
Chang Soo Suh et al., “High Breakdown Enhancement Mode GaN-Based HEMTs With Integrated Slant Field Plate”, U.S. Appl. No. 60/822,886, filed Aug. 18, 2006, 16 pp.
Chang Soo Suh et al., “III-Nitride Devices with Recessed Gates”, U.S. Appl. No. 60/972,481, filed Sep. 14, 2007, 18 pp.
Umesh Mishra et al., “Growing N-polar III-nitride Structures”, U.S. Appl. No. 60/972,467, filed Sep. 14, 2007, 7 pp.
Siddharth Rajan et al., “N-Polar Aluminum Gallium Nitride/Gallium Nitride Enhancement-Mode Field Effect Transistor”, U.S. Appl. No. 11/523,286, filed Sep. 18, 2006, 24 pp.
Chang Soo Suh et al., “Enhancement Mode Gallium Nitride Power Devices”, U.S. Appl. No. 11/856,687, filed Sep. 17, 2007, 58 pp.
Yuvaraj Dora et al., “ZrO2gate dielectrics produced by ultraviolet ozone oxidation for GaN and AlGaN/GaN transistors”, Mar./Apr. 2006, J. Vac. Sci. Technol. B 24(2), pp. 575-581.
Xing Gu et al., “AlGaN/GaN MOS transistors using crystalline ZrO2as gate dielectric”, 2007, Proceedings of SPIE, vol. 6473, 64730S, 8 pp.
S. Sugiura et al., “Enhancement-mode n-channel GaN MOSFETs fabricated onp-GaN using HfO2as gate oxide”, Aug. 16, 2007, Electronics Letters, vol. 43 No. 17, 2 pp.
W. Wang et al., “Comparison of the effect of gate dielectric layer on 2DEG carrier concentration in strained AlGaN/GaN heterostructure”, 2005, Mater. Res. Soc. Symp. Proc. vol. 831, 6 pp.
Ruonan Wang et al., “Enhancement-Mode Si3N4/AlGaN/GaN MISHFETs”, Oct. 2006; IEEE Electron Device Letters, vol. 27 , No. 10, pp. 793-795.
Y. Ando et al., “10-W/mm AlGaN-GaN HFET With a Field Modulating Plate”, May 2003, IEEE Electron Device Letters, vol. 24, No. 5, pp. 289-291.
V. Kumar et al., “High transconductance enhancement-mode AlGaN/GaN HEMTs on SiC substrate”, Nov. 27, 2003, Electronics Letters, vol. 39, No. 24, 2 pp.
Bruce M. Green et al., “The Effect of Surface Passivation on the Microwave Characteristics of Undoped AlGaN/GaN HEMT's”, Jun. 2000, IEEE Electron Device Letters, vol. 21, No. 6, pp. 268-270.
Umesh K. Mishra et al., “AlGaN/GaN HEMTs—An Overview of Device Operation and Applications”, Jun. 2002, Proceedings of the IEEE, vol. 90 , No. 6, pp. 1022-1031.
Marco Fanciulli et al., “Structural and Electrical Properties of HfO2Films Grown by Atomic Layer Deposition on Si, Ge, GaAs and GaN”, 2004, Mat. Res. Soc. Symp. Proc. vol. 786, pp. E6.14.1-E6.14.6.
Robert L. Coffie, Characterizing and Suppressing DC-to-RF Dispersion in AlGaN/GaN High Electron Mobility Transistors, 2003, PhD Thesis, University of California, Santa Barbara, 169 pp.
Shreepad Karmalkar et al., “Very high voltage AlGaN/GaN high electron mobility transistors using a field plate deposited on a stepped insulator”, 2001, Solid-State Electronics, 45, pp. 1645-1652.
International Search Report and Written Opinion for Application No. PCT/US2008/085031, dated Jun. 24, 2009, 11 pages.
Authorized officer Yolaine Cussac, International Preliminary Report on Patentability for Application No. PCT/US2008/085031, mailed Jun. 24, 2010, 6 pages.

Affiliated with

Also associated with

Rating

Insulated gate e-mode transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Insulated gate e-mode transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Insulated gate e-mode transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4182888