Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with other solid-state active device in integrated...
Utility Patent
1998-03-04
2001-01-02
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with other solid-state active device in integrated...
C257S140000, C257S341000, C257S378000
Utility Patent
active
06169300
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an Insulated Gate Bipolar Transistor with a high dynamic ruggedness.
2. Discussion of the Related Art
Known Insulated Gate Bipolar Transistors (IGBTs) include a heavily doped semiconductor substrate of a first conductivity type, for example of the P type, forming the collector of the device, over which a lightly doped semiconductor layer of the opposite conductivity type (N type) is formed. Inside the N type layer a plurality of elementary vertical MOSFETs is formed, each including a P type body region and an N type emitter region formed therein.
The IGBT is thus a four-layer device, and associated therewith is a thyristor. The most important feature of IGBTs over power MOSFETs is the low output resistance, which is achieved thanks to the conductivity modulation of the lightly doped N type layer by means of the injection therein of minority carriers from the P type substrate. Conventionally, the performance of an IGBT is measured by four electrical parameters: the collector-to-emitter saturation voltage (V
CESAT
), which is directly related to the output resistance and provides a measure of the energy dissipated by the IGBT in on state, the breakdown voltage between collector and emitter (BV
CES
), the latching current (I
latch
), and the fall-time when the device is switched off (t
fall
), which provides a measure of the energy dissipated by the IGBT when switched off.
The optimization of a generic one of said parameters generally leads to the degradation of one or more of the others. For example, trying to improve t
fall
and I
latch
causes a significant increase of V
CESAT
. In fact, it has been verified that notwithstanding the conductivity modulation effect of the lightly doped N type layer, the voltage drop caused by the so-called JFET component of the output resistance is substantial. This is due to the fact that not all of the minority carriers injected into the lightly doped N type layer from the substrate reach the surface of the device, some of them recombining in the lightly doped N type layer before they reach the surface thereof. For example, in a device with an N type layer 60 um thick and having a dopant concentration of 1E14 atoms/cm3, thanks to the conductivity modulation effect the dopant concentration in the N type layer at the junction with the substrate is approximately 1E16 atoms/cm3 but only of 1E15 atoms/cm3 at the top surface of the N type layer.
To improve BV
CES
and I
latch
, the distance between the elementary vertical MOSFETs forming the IGBT (i.e., the distance between the body regions) should be reduced. However, this would cause a substantial increase of the JFET component of the output resistance. On the contrary, increasing the distance between the body regions would reduce the JFET component of the output resistance, but at the cost of a degradation of BV
CES
and I
latch
.
A low value of I
latch
means that the device is easily subject to latch-up. Latch-up can most easily occur during switching: the voltage drop across the base and emitter of the parasitic NPN transistor, caused by the hole current flowing in the body region under the emitter region, turns the parasitic NPN transistor on, thus triggering the parasitic thyristor on. The voltage drop across the emitter and base of the NPN parasitic transistor depends on the resistance of the body region under the emitter region, and on the current of holes which, injected into the N type layer from the substrate, are collected by the body region of the IGBT. Triggering on of the parasitic thyristor can also lead to the destruction of the IGBT.
In view of the state of the art described, it is an object of the present invention to provide an IGBT structure having a high ruggedness, i.e. a high I
latch
value even in switching conditions, that is achieved without deterioration of the other electrical parameters characterizing the performance of the device.
SUMMARY OF THE INVENTION
According to the present invention, this and other objects are achieved by means of an Insulated Gate Bipolar Transistor comprising a semiconductor substrate of a first conductivity type forming a first electrode of the device, a semiconductor layer of a second conductivity type superimposed over said substrate, a plurality of body regions of the first conductivity type, a first doped region of the second conductivity type formed inside each body region, an insulated gate layer superimposed over portions of the semiconductor layer between the body regions and forming a control electrode of the device, a conductive layer insulatively disposed over the insulated gate layer and contacting each body region and each doped region formed therein, the conductive layer forming a second electrode of the device, wherein in said portions of the semiconductor layer between the body regions, second doped regions of the first conductivity type are formed and openings are provided in the insulated gate layer at said second doped regions to allow the conductive layer to contact the second doped regions.
Thanks to the fact that said second doped regions of the first conductivity type are provided in the portions of the second conductivity type semiconductor layer between the body regions, and thanks to the fact that said second doped regions are electrically connected to the body regions and to the emitter regions of the IGBT, each elementary IGBT is shunted by a bipolar junction transistor (BJT) formed by the second doped region, the semiconductor layer and the substrate; such a BJT provides a current path parallel to that of the parasitic transistor formed by the first doped regions, the body regions and the semiconductor layer, thus subtracting current therefrom. The voltage drop across the base-emitter junction of said parasitic transistor is thus reduced, and the triggering point of the parasitic thyristor is elevated.
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Patent Abstracts of Japan, vol. 012, No. 425 (E-681), Jul. 07, 1988 & JP-A-63 164473 (Fujitsu Ltd.)
Eckert II George C.
Galanthay Theodore E.
Morris James H.
Saadat Mahshid
SGS--Thomson Microelectronics S.r.l.
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