Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With switching speed enhancement means
Reexamination Certificate
2001-02-23
2002-09-10
Chaudhuri, Olik (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
With switching speed enhancement means
C257S169000, C257S168000, C257S148000
Reexamination Certificate
active
06448588
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power semiconductor device, and more particularly, to an insulated gate bipolar transistor having a high breakdown voltage in a reverse blocking mode and a method for fabricating the same.
2. Description of the Related Art
Recently, an insulated gate bipolar transistor as a new power semiconductor device having high-speed switching characteristics of a high power MOS field effect transistor (MOSFET) and much power characteristics of a bipolar junction transistor (BJT), is very important.
FIG. 1
is a schematic sectional view of the structure of a conventional insulated gate bipolar transistor, and
FIG. 2
is a graph illustrating concentration (marked a thin solid line) and a field distribution (marked a thick solid line) on each layer of the insulated gate bipolar transistor of FIG.
1
. In
FIG. 2
, reference numerals “I”, “II”, “III”, and “IV” denote a p
+
semiconductor substrate
11
, a n
+
buffer layer
12
, a n
−
epitaxial layer
13
, and a p
+
base region
15
, respectively.
Referring to
FIG. 1
, a region having a high concentration of second conductivity type impurities, for example, a n-type (hereinafter referred to as n
+
) buffer layer
12
is formed on a region having a high-concentration of first conductivity type impurities used as a collector region, for example, on a p-type (hereinafter referred to as p
+
) semiconductor substrate
11
. A low-concentration n-type (hereinafter referred to as n
−
) drift region
13
is formed on the n+buffer layer
12
. The n
−
drift region
13
can be formed by an epitaxial growth method. A p
+
base region
14
by the selective diffusion of p-type impurities is formed on a predetermined region of the upper surface of the n
−
drift region
13
, and a n
+
emitter region
15
by the selective diffusion of n-type impurities is formed on a predetermined region of the upper surface of the p
+
base region
14
.
A gate dielectric layer
16
is formed so as to cover a channel region of the p
+
base region
14
between the upper surface of the n
−
drift region
13
and the upper surface of the n
+
emitter region
15
. A gate electrode
17
formed of a polysilicon layer is formed on the gate dielectric layer
16
. An emitter electrode
18
is formed so as to be electrically connected to the n-type emitter region, and a collector electrode
19
is formed on a lower region of the p
+
semiconductor substrate
11
. The gate electrode
17
and the emitter electrode
18
are insulated each other by an oxide film (not shown) functioning as an interdielectric layer.
In the conventional insulated gate bipolar transistor having the above structure, the n
+
buffer layer
12
exists for the reason why a reverse voltage is applied between the n
−
drift region
13
and the p
+
base region
14
in a forward blocking mode in which the gate electrode
17
and the emitter electrode
18
are short-circuited and a positive (+) voltage with respect to the emitter electrode
18
is applied to the collector electrode
19
, as this happens, so that a depletion layer formed on a junction between the two regions
13
and
14
may not extend to the p
+
semiconductor substrate
11
. Thus, the thickness of the n
−
drift region
13
can be reduced by the n
+
buffer layer
12
, as a result, on-state losses of a device can be reduced. During a forward conduction (in a case where a predetermined voltage is applied to the gate of the device, and then a channel is formed), the higher the concentration of the n
+
buffer layer
12
is and the larger the thickness of the n
+
buffer layer
12
is, hole injection from the p
+
semiconductor substrate
11
to the n
−
drift region
13
is suppressed, and then, the switching speed of the device is increased.
However, due to the n
+
buffer layer
12
, the breakdown voltage level of the device is decreased in a reverse blocking mode in which a voltage is not applied to the gate electrode
17
and a negative (−) voltage with respect to the emitter electrode
18
is applied to the collector electrode
19
.
More specifically, as shown in
FIG. 2
, it is evident that the concentration of the n
+
buffer layer
12
is high, and as described previously, this is the reason why the larger the concentration of the buffer layer, the more the switching characteristics of the device are improved, and the larger a forward voltage drop is during a forward conduction. Likewise, in the insulated gate bipolar transistor using the n
+
buffer layer
12
, since the breakdown voltage level which can obtained in a forward blocking mode is the same as the area of a trapezoid drawn by a field distribution, a high breakdown voltage can be obtained. However, the breakdown voltage level which can be obtained in a reverse blocking mode is small as the size of a triangle (A
1
of
FIG. 2
) drawn by the field distribution.
That is, in the reverse blocking mode, the larger the slope of the field is, the higher the concentration of the n
+
buffer layer
12
is, and the higher the concentration of the n
+
buffer layer
12
is, the smaller the size of the triangle (A
1
of
FIG. 2
) is. Accordingly, the larger the concentration of the n
+
buffer layer
12
is, the smaller the breakdown voltage in the reverse blocking mode is.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide an insulated gate bipolar transistor in which the improved electrical characteristics of a device obtained by a high doping concentration buffer layer can be maintained, and a high breakdown voltage can be maintained in a reverse blocking mode.
It is another object of the present invention to provide a method for fabricating the insulated gate bipolar transistor.
Accordingly, to achieve the above object, there is provided an insulated gate bipolar transistor. The insulated gate bipolar transistor includes a semiconductor substrate having a high concentration of first conductivity type impurities, a buffer layer formed of an upper buffer layer having a first doping concentration of second conductivity type impurities, which is formed over the semiconductor substrate, and a lower buffer layer having a second doping concentration lower than the first doping concentration, which is formed between the upper buffer layer and the semiconductor substrate, a drift region of a second conductivity type formed on the upper buffer layer, a base region of a first conductivity type formed in a predetermined region of the drift region, an emitter region of a second conductivity type formed in the surface of a predetermined region of the base region, a gate dielectric layer formed on a channel region of the base region, a gate electrode formed on the gate dielectric layer, an emitter electrode formed so as to be electrically connected to the emitter region, and a collector electrode formed so as to be electrically connected to the semiconductor substrate.
Preferably, the first doping concentration of the upper buffer layer is 10
16
~10
18
cm
−3
, and the second doping concentration of the lower buffer layer is 10
12
~10
15
cm
−3
.
Preferably, the conductivity type of the lower buffer layer is first conductivity type impurities or second conductivity type impurities, and more particularly, the conductivity type of the lower buffer layer is substantially intrinsic.
In order to achieve another object, according to one aspect of the present invention, there is provided a method for fabricating an insulated gate bipolar transistor. The method for fabricating an insulated gate bipolar transistor comprises the steps of: preparing a semiconductor substrate having a high concentration of first conductivity type impurities; sequentially-forming a lower buffer layer having a first doping concentration on the semiconductor substrate and an upper buffer layer hav
Kim Soo-seong
Kwon Young-dae
Yun Chong Man
Fairchild Korea Semiconductor Ltd.
Huynh Yennhu B.
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