Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
1997-08-26
2002-09-17
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S142000, C257S168000, C257S172000, C257S342000, C257S399000, C257S913000
Reexamination Certificate
active
06452219
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based on and claims priority of Japanese Patent Application No. Hei. 8-240559 filed on Sep. 11, 1996, the content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an insulated gate bipolar transistor (IGBT).
2. Description of Related Art
FIG. 5
shows a portion of a conventional IGBT. As shown in
FIG. 5
, an n
−
type layer
2
is disposed above a p type semiconductor substrate
1
, and p type base areas
3
are partly formed in the n
−
type layer
2
to form a plurality of IGBT unit cells at the face of the n
−
type layer. At the face of the p type base area
3
of each unit cell is formed an n
+
type source area
4
and thereby a channel area is defined at the face of the p type base area
3
between the n
−
type layer
2
and the n
+
type source area
4
in each unit cell. A common gate electrode
6
is disposed for the IGBT unit cells to overlap with the respective channel areas. The common gate electrode
6
is covered with interlayer insulation film
7
.
A common source electrode
8
contacts both the base area
3
and the source area
4
in each unit cell, and a common drain electrode
9
which supplies a drain current is disposed on a back side of the semiconductor substrate
1
. A n
+
type buffer layer
10
is disposed between the semiconductor substrate
1
and the n
−
type layer
2
; this buffer layer
10
is for shortening the turn-on time of the IGBT
100
and for preventing a latch up from occurring by interrupting injections of holes from the semiconductor substrate
1
to the n
−
type layer
2
.
FIGS. 6A and 6B
show an operation of a circuit using the IGBT
100
as a switch for actuating a load disposed in a vehicle.
As shown in
FIG. 6A
, the IGBT
100
is connected in series to a load
101
, for instance an ignition coil, and actuates the load
101
when power is supplied thereto from a battery
102
via an ignition switch
103
. An inductive load
104
is connected to a power line extending from the battery
102
in parallel to the IGBT
100
and the load
101
.
As shown in
FIG. 6B
, when the ignition switch
103
is turned off, a negative voltage resulting from a reverse voltage of inductive load
104
may be induced on the power line, and a noise voltage whose magnitude is between −100V and −200V may be applied to the drain electrode
9
of the IGBT
100
. A withstanding voltage in the IGBT
100
against a positive voltage depends on a pn junction formed between the n
−
type layer
2
and the p type base area. A withstanding voltage in the IGBT
100
against a negative voltage depends on a pn junction formed between the semiconductor substrate
1
and the buffer layer
10
.
Conventionally, the n
+
type buffer layer
10
is formed entirely on a wafer and the IGBT
100
is always constructed as a semiconductor chip by dicing the semiconductor wafer as shown in FIG.
5
. Accordingly, the buffer layer
100
is bare at the edge of a cross-section formed by dicing of the semiconductor wafer. Crystallinity at the edge of the cross-section is rough because of dicing, and the pn junction at the edge of the cross-section includes crystal defects and is unstable. Therefore, the withstanding voltage of the pn junction at the edge of the cross-section is drastically decreased, and when the negative voltage is applied to the IGBT
100
, breakdown occurs at a portion where the withstanding voltage of the pn junction is lowest on the edge of the cross-section (i.e., a portion surrounded by a broken line in FIG.
5
). Thus, energy caused by the negative voltage localizes at the edge portion, and the IGBT
100
may be destroyed by heat resulting from voltage localization.
SUMMARY OF THE INVENTION
In view of the above problems of the related art, an object of the present invention is to prevent an IGBT from breaking down at an edge portion when a negative voltage is applied to the IGBT, and to improve a withstanding voltage against a negative voltage.
In order to accomplish the above-described object, according to the present invention, a buffer layer made of a second conductivity type semiconductor is located between a first layer and a second layer not to bare an edge of a diced cross-section of a chip. In general, the higher the impurity concentration, the lower the withstand voltage because a withstand voltage of a pn junction is determined by impurity concentration at the pn junction; when the buffer layer is not bare at the edge of the diced cross-section as described in the present invention, the withstand voltage of the pn junction between a semiconductor substrate and the buffer layer can be lower than the withstand voltage of the pn junction at the edge of a diced cross-section even if the pn junction at the edge of the diced cross-section includes crystal defects due to the dicing.
Therefore, the whole pn junction between the semiconductor substrate and the buffer layer, which has a wide area, breaks down; as a result, energy caused by a negative voltage is absorbed, and the withstanding voltage against the negative voltage is improved.
Preferably, the buffer layer is formed as a mesh shape or an island shape.
REFERENCES:
patent: 4928155 (1990-05-01), Nakagawa et al.
patent: 4985741 (1991-01-01), Bauer et al.
patent: 4989058 (1991-01-01), Colak et al.
patent: 5519245 (1996-05-01), Tokura et al.
patent: 5723882 (1998-03-01), Okabe et al.
patent: 5753943 (1998-05-01), Okabe et al.
patent: 5994189 (1999-11-01), Akiyama
patent: 004104588 (1991-08-01), None
patent: 0503605 (1992-09-01), None
patent: 000522670 (1993-01-01), None
patent: 0622853 (1994-11-01), None
patent: 64-54765 (1989-03-01), None
patent: 64-81270 (1989-03-01), None
patent: 64-82565 (1989-03-01), None
patent: 64-82566 (1989-03-01), None
patent: 64-90561 (1989-04-01), None
patent: 1-282872 (1989-11-01), None
patent: 402036561 (1990-02-01), None
patent: 2-112285 (1990-04-01), None
patent: 404192366 (1992-07-01), None
patent: 4-66110 (1992-10-01), None
patent: 5-78949 (1993-10-01), None
patent: 5-275688 (1993-10-01), None
patent: 6-80831 (1994-10-01), None
patent: 7-226514 (1995-08-01), None
Kato Naohito
Kawakita Haruo
Miyase Yoshiyuki
Okabe Naoto
Denso Corporation
Harness Dickey & Pierce PLC
Loke Steven
Nadav Ori
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