Insulated gate bipolar transistor

Details Insulated gate bipolar transistor Insulated gate bipolar transistor

2000-10-06

2002-05-07

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

With extended latchup current level

Reexamination Certificate

active

06384431

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based upon Japanese Patent Application No. Hei. 11-288249 filed on Oct. 8, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to insulated gate bipolar transistors, and particular to an insulated gate bipolar transistor having a buffer layer between a collector layer and a base layer in a substrate.
2. Related Art
In a case of power devices used for inverter circuits in a driving circuit which switches a motor or the like, surge voltage may be applied due to an inductance component when the power is turned off. In this case, the power device may be damaged. When an insulated gate bipolar transistor (IGBT) is used as the power device, since sustain characteristic during breakdown indicates negative characteristic, current may be locally concentrated during the breakdown, and therefore the inherent characteristic of the IGBT may facilitate causing the damage. Since the surge voltage caused during the turning off of the IGBT may causing the damage, some countermeasures have been taken.
For example, JP A 6-268226 discloses one IGBT. As shown in
FIG. 11
, an n-type buffer layer
2
, an n-type intermediate layer
3
, and an n-type base layer
4
are formed in this order on a p-type semiconductor substrate
1
. A p-type well layer
5
and a high concentration n-type emitter layer
6
are sequentially formed in the n-type base layer
4
. Furthermore, a gate insulating film
7
and each electrode are formed. The n-type intermediate layer
3
has an impurity concentration between that of the buffer layer
2
and that of the n-type base layer
4
each of which sandwiches the n-type buffer layer
2
. Distribution of the impurity concentration along a depth direction from the emitter surface is shown in FIG.
12
B.
According to this structure, while an L-load is turned off, when a depletion region spreading in the n-type base layer
4
reaches the n-type intermediate layer
3
, the spread of the depletion region is restricted. Since the impurity concentration of the n-type intermediate layer
3
is lower than that of the n-type buffer layer
2
,it can restrain abrupt decreasing of current. Then,the surge voltage can be reduced.
FIG. 12A
shows the distribution of the electric field E from the emitter surface, when the breakdown starts according to the related art shown in FIG.
11
.
However, in the case where the n-type intermediate layer
3
is provided in this way, the depletion layer may reach the n-type buffer layer
2
from the n-type base layer
4
through the n-type intermediate layer
3
during turning off by the L-load. In such a situation, even if the n-type intermediate layer
3
is formed, a boundary of the depletion layer has reached the n-type buffer layer
2
at the breakdown timing, the negative characteristic of the sustain characteristic increase, and therefore a breakdown with stand voltage may lower.
SUMMARY OF THE INVENTION
This invention has been conceived in view of the background thus far described and its first object is to provide insulated gate bipolar transistors which can restrain causing surge voltage due to an inductance component while an L-load is turned off.
Its second object is to provide insulated gate bipolar transistors which can improve a negative characteristic of a sustain voltage during breakdown.
Its third object is to provide insulated gate bipolar transistors which can restrain causing surge voltage due to an inductance component while an L-load is turned off and can improve a negative characteristic of a sustain voltage during breakdown.
According to the present invention, the third semiconductor layer has a predetermined impurity concentration and a predetermined thickness so that a depletion region expanding from a side of the fourth semiconductor layer stops before the depletion region reaches the second semiconductor layer, at a time of a breakdown. In this structure, a space charge density as a result of depletion is lowered. When breakdown current increases, space charges which are cancelled by carriers injected from the first semiconductor layer decrease. Thus a sustain characteristic can be improved.


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