Data processing: measuring – calibrating – or testing – Measurement system – Measured signal processing
Reexamination Certificate
2002-10-10
2004-08-24
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system
Measured signal processing
C327S154000, C375S337000, C369S047320, C369S126000
Reexamination Certificate
active
06782353
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a measuring device measuring characteristics of a data transmission system with high accuracy and a clock regenerating circuit used therein, and in particular, to a measuring device adopting a technique for correctly regenerating a clock signal, from a data signal formed from RZ method bit codes, even during a period in which the data signal continues for a plurality of bits at the same level, and measuring, with high accuracy, the error ratio, jitter, wander characteristics, or the like accompanying transmission of the data signal, and to a clock regenerating circuit used therein.
BACKGROUND ART
Generally, in a data transmission system transmitting data signals or a measuring device or the like carrying out measurement of the jitter characteristic or the like of the data transmission system, the codes of the data signal are read and measurement of the jitter or wander characteristic is carried out, by a clock signal regenerated from the data signal.
FIG. 9
is a block diagram showing a configuration of a conventional clock regenerating circuit
10
used in such a measuring device.
In
FIG. 9
, a data converter
11
converts data signal Da inputted by the NRZ (Non Return to Zero) method to data signal Db of the RZ (Return to Zero) method.
Here, the RZ method is a method once returning the amplitude of the data signal to a reference level between some bit code and the next bit code.
Further, the NRZ method is a method not returning the amplitude of the data signal to the reference level between some bit code and the next bit code.
Further, in usual data transmitting systems, transmission of data is carried out by the NRZ method is since variations of the level are few even in the case of the similar code array.
The data converter
11
generates and outputs a pulse of a predetermined width synchronized with the rising timing of the data signal Da inputted by the NRZ method and the inverted signal of the data signal Da.
For example, as shown in
FIG. 10A
, when the NRZ method data signal Da corresponding to a code array of 0, 1 is inputted, as shown in
FIG. 10B
, the RZ method data signal Db, formed from a pulse train having a predetermined width synchronized with the rise and fall of the data signal Da, is outputted from the data converter
11
.
Here, the data signal Db, within a period in which the codes of the data signal Da are inverted at each bit, is a pulse train which rises to a high level and returns to a low level at each code.
Further, the data signal Db, within a period in which the codes of the data signal Da are equal and continue, keeps a low level.
Accordingly, if the data signal Db is used as a clock signal, the clock signal is absent for the period in which the codes of the data signal Da are equal and continue.
If there is such an absence period, there is the problem that operation at the side of another circuit using the clock signal cannot be ensured.
Therefore, in a conventional clock regenerating circuit
10
, as shown in
FIG. 9
, due to a delay adding circuit
12
being provided at a subsequent stage of the data converter
11
, absence of the clock signal as described above is compensated for.
In an OR circuit (adding circuit)
12
b
, the delay adding circuit
12
logically-adds the data signal Db outputted by the RZ method from the data converter
11
and a signal Db′ in which the data signal Db is delayed by a predetermined time T by a delay circuit
12
a
, and outputs them.
Here, for example, the delay time T of the delay circuit
12
a
is set to an integer multiple of a period Tc of the clock signal to be regenerated. For example, if the delay time T=Tc, the data signal Db′, in which the data signal Db is delayed by one clock as shown in
FIG. 10C
, is outputted from the delay circuit
12
a.
Further, as shown in
FIG. 10D
, the logical sum of the data signal Db and the data signal Db′, in which the data signal Db is delayed by one clock, is outputted from the OR circuit
12
b.
The output shown in
FIG. 10D
is a signal where pulses are inserted one by one in each period in which a pulse train is not outputted in FIG.
10
B. If this is made to be the clock signal, the absence periods can be eliminated or shortened.
However, as described above, when the delay time T of the delay circuit
12
a
of the delay adding circuit
12
is set to the period Tc of the clock signal as described above, because only one pulse can be supplemented at the head of each absence period, there is the problem that the effect of shortening the absence period is low.
In order to resolve the above, further shortening of the absence period of the clock signal by providing the delay adding circuit
12
at a plurality of steps in series as a clock regenerating circuit
10
′ shown in
FIG. 11
, is considered.
However, there are the problems that, here, the configuration as the clock regenerating circuit becomes complicated, and further, phase fluctuations occur in the regenerated clock signal due to variations or dispersion of the delay time T in each step, and identification of data and measurement of jitter or the like by the clock signal cannot be correctly carried out.
On the other hand, in Jpn. Pat. Appln. KOKAI Publication Nos. 11-313052 and 2000-197049, clock regenerating circuits are disclosed, regenerating a clock signal by using a band-pass filter having a predetermined band characteristic for extracting a clock signal component from an inputted data signal, and a saturation amplifier or an AGC amplifier amplifying the clock signal component extracted by the band-pass filter to a predetermined level.
However, if a portion, in which the same code component continues markedly, exists in the data signal inputted to such a clock regenerating circuit, in the clock signal outputted from the band-pass filter, as shown in
FIG. 12A
, in addition to an original clock signal component a, various noise components b, c, d, e, or the like based on relaxation vibrations at the interior of the band-pass filter described later are superposed and appear.
Here, relaxation vibrations at the interior of the band-pass filter are, when a period in which the same code component continues extremely exists in the data signal, a vibration phenomenon at the interior of the band-pass filter with respect to the data signal inputted until immediately before that period, as shown in FIG.
12
B.
Such various noise components b, c, d, e, or the like based on relaxation vibration at the interior of the band-pass filter appear during the period when relaxation vibrations exist.
The relaxation vibration at the interior of the band-pass filter depends on wideness
arrowness of the band characteristic of the band-pass filter.
Namely, when the band characteristic of a band-pass filter extracting, from a data signal transmitted at a predetermined carrier wave frequency, a signal component having the same frequency as the clock signal to be regenerated, is regulated to a narrow band characteristic in accordance with the aforementioned predetermined carrier wave frequency, relaxation vibration at the interior of the band-pass filter markedly appears.
In accordance therewith, in the clock signal outputted from the saturation amplifier or the AGC amplifier, as shown in
FIG. 12C
, in addition to the original clock signal component a′, various noise components b′, c′, d′, e′, or the like are superposed and appear.
Further, in the period in which relaxation vibration at the interior of the band-pass filter exists, such a saturation amplifier or AGC amplifier works in a non-saturation region as shown in FIG.
12
C.
Therefore, the device of the saturation amplifier or the AGC amplifier merely carries out waveform shaping, and the output in the period in which relaxation vibration at the interior of the band-pass filter exists is not identified as a clock signal. Therefore, the device has not the same code tolerance.
As a result, in the clock regenerating circuit regenerating the clock signal by using such a
Anritsu Corporation
Barlow John
Le John
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