Data processing: structural design – modeling – simulation – and em – Emulation – Of instruction
Reexamination Certificate
2008-07-29
2008-07-29
An, Meng-Ai (Department: 2195)
Data processing: structural design, modeling, simulation, and em
Emulation
Of instruction
C703S023000, C703S027000, C703S028000, C711S156000
Reexamination Certificate
active
11006414
ABSTRACT:
Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.
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Andress Sidney L.
Guenthner Russell W.
Heath John E.
An Meng-Ai
Bull HN Information Systems Inc.
Guenthner Russell W.
Phillips James H
To Jennifer N
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