Instruction to normalize redundantly encoded floating point numb

Details Instruction to normalize redundantly encoded floating point numb Instruction to normalize redundantly encoded floating point numb

1995-11-27

2000-11-28

Ngo, Ohuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

748495, G06F 700, G06F 738

Patent

active

061547603

ABSTRACT:
The present invention is an apparatus to normalize a floating point number. The apparatus has a first storage area comprising the floating point number. The floating point number comprises an exponent field and an explicit bit. The apparatus further comprises a circuit to normalize the floating point number when the explicit bit is not set and the exponent field has a first predetermined value identifying a redundant denormal encoding of the floating point number. Otherwise the encoding of the number is not changed by the circuit.

REFERENCES:
patent: 4991130 (1991-02-01), Kojima
patent: 4994996 (1991-02-01), Fossum et al.
patent: 5357237 (1994-10-01), Bearden et al.
patent: 5481686 (1996-01-01), Dockser
patent: 5504912 (1996-04-01), Morinaga et al.

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