Instruction supplying apparatus with a branch target buffer havi

Details Instruction supplying apparatus with a branch target buffer havi Instruction supplying apparatus with a branch target buffer havi

1995-10-03

1998-04-14

Lim, Krisna

395581, 395580, G06F 900, G06F 932

Patent

active

057404151

ABSTRACT:
A branch execution unit processes operand data which is supplied from an instruction decoder with branch instruction information which is read from a branch target buffer, carries out branch prediction and execution, and forms a branch probability flag which is generated in relation to a branch instruction for supplying to a branch target buffer registration/update decision mechanism. In registration of a branch instruction which is non-registered in the BTB registration/update decision mechanism, the registration or non-registration is carried out in accordance with the value of the branch probability flag. Thus, it is possible to prevent a branch instruction having a low branch probability from being registered in the branch target buffer, thereby preventing reduction of branch prediction accuracy. The branch prediction is executed with employment of only a validity bit. Thus provided is an instruction processing apparatus including a branch target buffer which can be readily constructed with high branch prediction accuracy and causes no cycle penalty upon registration of a branch instruction or updating of the content thereof.

REFERENCES:
patent: 5530825 (1996-06-01), Black et al.
patent: 5584001 (1996-12-01), Hoyt et al.
patent: 5628021 (1997-05-01), Iadonato et al.
"Branch Prediction Strategies and Branch Target... ", J.K. F. Lee et al., IEEE, Computer vol. 15, No. 1, Jan. 1984, pp. 6-22, cited on page four of the specification.
"Computer Architecture: Quantative Approach", D. A. Patterson, Morgan-Kaufman Publishers, published 1990, pp. 307-314.

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