Instruction storage and cache miss recovery in a high speed mult

Details Instruction storage and cache miss recovery in a high speed mult Instruction storage and cache miss recovery in a high speed mult

1991-05-30

1993-01-12

Kriess, Kevin A.

Boots, shoes, and leggings

364DIG1, 3642434, 36424341, 364243, 3642599, 3642597, 364259, 36426281, 3642624, 3642606, 3642604, G06F 1208

Patent

active

051796805

ABSTRACT:
A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

REFERENCES:
patent: 3694813 (1972-09-01), Loh et al.
patent: 3805254 (1974-04-01), Schuur
patent: 4064559 (1977-12-01), Kawanabe
patent: 4327379 (1982-04-01), Kadakia et al.
patent: 4371951 (1983-02-01), Kort et al.
patent: 4400791 (1983-08-01), Kitado
patent: 4433377 (1984-02-01), Eustis et al.
patent: 4437149 (1984-03-01), Pomerene et al.
patent: 4464650 (1984-08-01), Eastman et al.
patent: 4494151 (1985-01-01), Liao
patent: 4545032 (1985-10-01), Mak
patent: 4593267 (1986-06-01), Kuroda et al.
patent: 4644545 (1987-02-01), Gershenson
patent: 4933837 (1990-06-01), Freidin
Fisher, "The VLIW Machine: A Multiprocessor for Compiling Scientific Code", Computer, Jul. 1984 pp. 45-53.
Fisher et al., "Parallel Processing: A Smart Compiler and a Dumb Machine", Dept. of Computer Science, Yale University.
Riseman et al., "The Inhibition of Potential Parallelism by Conditional Jumps", IEEE Transactions on Computers, Dec. 1972, Short Notes pp. 1405-1415.
Fisher et al., "VLIW Machines: Multiprocessors We Can Actually Program", Dept. of Computer Science, Yale University.
Tjaden et al., "Detection and Parallel Execution of Independent Instructions", IEEE Transactions on Computers, vol C-19, No. 10 Oct. 1970, pp. 889-895.
Hack, "Peak vs. Sustained Performance in Highly Concurrent Vector Machines", Computer, Sep. 1986, pp. 11-19.
Amdahl, "Validity of the Single Processor Approach to Achieving Large Scale Computing Capabilities", Spring Joint Computer Conf., 1967 pp. 483-485.
Fisher, "The Optimization of Horizontal Microcode Within and Beyond Basic Blocks: An Application of Processor Scheduling with Resources", U.S. Dept of Energy Report, Mathematics and Computing, COO-3077-161.

Affiliated with

Also associated with

Rating

Instruction storage and cache miss recovery in a high speed mult does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Instruction storage and cache miss recovery in a high speed mult, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instruction storage and cache miss recovery in a high speed mult will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1226054