Instruction queue capable of changing the order of reading instr

Details Instruction queue capable of changing the order of reading instr Instruction queue capable of changing the order of reading instr

1997-05-22

1999-06-08

Lall, Parshotam S.

395392, G06F 938

Patent

active

059110589

ABSTRACT:
An instruction queue 80 maintains the CPI (clock cycles per instruction) and performance of a microprocessor that employs the instruction queue even if a branch instruction is executed. The queue 80 stores valid instructions in an instruction memory 810. When a branch instruction is supplied to the queue 80, the queue 80 detects instructions that are independent of the branch instruction in the memory 810, and an order controller 1300 puts the independent instructions behind the branch instruction in the memory 810. The queue 80 quickly finds a branch instruction, to let a cache start refilling speedily. While the cache is being refilled, the independent instructions put behind the branch instruction are executed to improve the CPI.

REFERENCES:
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patent: 5488729 (1996-01-01), Vegesna et al.
patent: 5511172 (1996-04-01), Kimura et al.
patent: 5684971 (1997-11-01), Martell et al.
patent: 5699537 (1997-12-01), Sharanppani et al.

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