Data processing: structural design – modeling – simulation – and em – Emulation – Of instruction
Reexamination Certificate
2007-05-22
2007-05-22
Rodriguez, Paul (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
Of instruction
C703S023000, C703S027000, C712S220000, C712S233000, C712S237000
Reexamination Certificate
active
10683029
ABSTRACT:
Techniques are described for emulating inter-processor communications between multiple instruction processors. The techniques provide inter-processor message accounting and error detection. A system, for example, includes software executing within an emulation environment provided by a computing system. The emulation software emulates an instruction processor having an interface to receive inter-processor messages. During emulation the emulated instruction processor calculates an actual count of the inter-processor messages received during emulation. A compiler executing on the computing system compiles test software to output an instruction stream for execution by the emulated instruction processor. The compiler calculates an expected count of inter-processor messages that the emulated instruction processor is expected to receive during emulation. Emulation control software executing on the computing system generates a report that presents the expected count of the inter-processor messages and the actual count of the inter-processor messages.
REFERENCES:
patent: 5889978 (1999-03-01), Jayakumar
patent: 6356997 (2002-03-01), Krishnan et al.
patent: 6370606 (2002-04-01), Bonola
patent: 6971103 (2005-11-01), Hokenek et al.
patent: 7065614 (2006-06-01), Vartti et al.
patent: 7096322 (2006-08-01), Sollom et al.
Svenson, A. “Software Primitives for Emulation of Multi-Processor Architectures”. Proc. of the 23rd Hawaii Int'l Conf. on System Science. vol. 1. pp. 48-56. Jan. 2-5, 1990.
Blough, D.M. et al. “Fault-Injection-Based Testing of Fault-Tolerant Algorithms in Message-Passing Parallel Computers.” 27th Int'l Symposium on Fault-Tolerant Computing. pp. 258-267. Jun. 24-27, 1997.
Cischke Christopher M.
Sollom Jason D.
Williams James A.
Johnson Charles A.
McMahon Beth L.
Rodriguez Paul
Sharon Ayal
Shumaker & Sieffert P.A.
LandOfFree
Instruction processor emulation having inter-processor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Instruction processor emulation having inter-processor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instruction processor emulation having inter-processor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3778283