Instruction processor control system using separate hardware and

Details Instruction processor control system using separate hardware and Instruction processor control system using separate hardware and

1994-08-09

1996-11-19

Donaghue, Larry D.

Boots, shoes, and leggings

395376, 364DIG1, 3642628, 3642624, 3642756, 3642631, G06F 972

Patent

active

055772595

ABSTRACT:
A digital instruction processor control system for an instruction processor having a multiple stage instruction execution pipeline capable of executing binary instructions in fixed predetermined stages. The control system includes a hardware controller to generate control signals for execution of all pipeline stages of standard instructions and for the first stage of extended cycle instructions and provides a main microcode controller to provide programmed control signals for controlling all subsequent stages of execution of extended cycle instructions. The control system also utilizes a separate sequence microcode controller for execution of certain instructions of a predetermined type including decimal instruction execution, during which time the main microcode controller is under control of the separate sequence controller.

REFERENCES:
patent: 4992934 (1991-02-01), Partanova et al.
patent: 5136696 (1992-08-01), Berkwith et al.
patent: 5222244 (1993-06-01), Carbine et al.
Myers et al. The 80960 Microprocessor Architecture; 1988; 159-183.
Bandyopadhyay et al, "Mirco-code RISC Architecture" Mar. 1987.
Bandyopadhyay et al "Combining Both Micro-Code and Hardwire Control in RISC, Computer Architecture News", Sep. 1987.
Hinton et al "Microarchitecture of the 80960 High Integration Processor" 1988.

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