Instruction processing method and system for variable-length ins

Details Instruction processing method and system for variable-length ins Instruction processing method and system for variable-length ins

1997-04-30

2000-02-08

Eng, David Y.

Electrical computers and digital processing systems: processing

Instruction decoding

G06F 930

Patent

active

060237562

ABSTRACT:
In an instruction processing system having a variable length instruction set, an instruction set which can no longer divided in an instruction set level architecture of a data processing system, is defined as an "elementary instruction set", and a combination of some number of elementary instruction sets is defined as a "parallel instruction set". When an instruction string fetched in an instruction fetch mechanism matches with one of some number of predetermined parallel instruction sets, instructions included in the parallel instruction set are issued or supplied to corresponding processing units, simultaneously in parallel. If the instruction string fetched in the instruction fetch mechanism matches with non of the predetermined parallel instruction sets, the instructions fetched in the instruction fetch mechanism are individually executed in the order for each elementary instruction set.

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